AN INTRODUCTION TO FASTBUS

FASTBUS is a sophisticated data acquisition system standard developed by the U.S. NIM Committee in collaboration with the European ESONE Committee (ANSI/IEEE STD 960-1986). FASTBUS was designed to keep features of older important standards while extending the capabilities of data acquisition systems. FASTBUS provides for a more densely packed system, reducing dramatically the per-input cost. This and other design goals have been achieved. FASTBUS meets the requirements of the next generation of data acquisition systems by incorporating several powerful features, including:

Essentially, the FASTBUS backplane is intended to be an extension of a computer backplane. By its nature, therefore, it is an expandable system. The backplane is called a "Segment". Connections between segments are made by an interface, called a Segment Interconnect (SI). An SI in one segment is connected to a SI in another segment by a Cable Segment. The Segment Interconnect can be either a Master or Slave, depending on the operation it is performing. Moreover, it can be a Master on the FASTBUS Segment and simultaneously a Slave on the Cable Segment. The designations Master and Slave here are dynamic, in that the designation is defined by the role played by the SI at some given time.

FASTBUS permits multiple masters to have access to the segment. The standard provides a protocol for arbitration when more than one master requests control of the segment. Once mastership is granted, the Master may then proceed to establish a communications "lock" with any other device on the segment which will act as a Slave. Alternatively, the Master may broadcast a message to all Slaves which respond to the broadcast (e.g., clear, polling for data ready, etc.).

The integrity of communication between Master and Slave modules is ensured via a handshaking scheme. This frees the standard from a speed requirement. That is, communication occurs at whatever speed the Master/Slave system will support. This, of course, is not the case with broadcast commands where a Master talks to all Slaves in a segment, nor is it true for hardware block transfers where the Master must be able to operate as fast as the fastest Slave. So while there are cautions required for use of FASTBUS, the versatility and expandability is sufficient to meet the most demanding requirements of data acquisition systems.

MECHANICS

The Crate

The crate is a standard rack-mountable package with 26 slots. The cooling and power supply systems are non-integral with the crate. Conventional forced air (fans) or water cooling may be used. Water cooling uses a heat exchanger to chill the forced air and is less commonly used. The FASTBUS power standard allows for +5 V, -5.2 V, -2 V, ±15 V and +28 V supplies. In commercial units, the ±15 V and +28 V are infrequently used, with +28 V being the least common. Care should be taken to assure that the proper voltages are available in any given crate.

The backplane of the FASTBUS crate consists of two parts, the Segment and the Auxiliary Backplane. The FASTBUS Segment is the high-speed digital data bus of the system. It provides for the control and flow of data. On the rear of the crate are two cards are called Ancillary Logic. The Geographical Address Control card (GAC) is used to terminate the FASTBUS signal lines with 100 W resistors. It should be located in either slot 24 or 25 on the rear side of the FASTBUS backplane. The Arbitration Timing Control card (ATC) supplies the required timing signals for bus arbitration and broadcast addressing. It should be located in either slot 0 or slot 1 on the rear side of the FASTBUS backplane and also terminates the bus in 100 W.

The Auxiliary Backplane is not normally employed for the transfer of data. It is used to implement optional features such as analog outputs to trigger logic, rear-panel inputs or custom I/O.

FASTBUS DATA TRANSFER

Because a segment may contain more than one Master, FASTBUS provides for arbitration between them to determine the order in which they will gain control over the bus. The Master asynchronously requests use of the Segment, specifying the priority of the request. This initiates an arbitration cycle. Upon obtaining mastership, it performs its operations.

The FASTBUS Segment includes a 32-bit wide data bus, used both for data and for addressing. Any slot within a FASTBUS crate can contain a Master. For this reason, sophisticated addressing schemes have been implemented in FASTBUS. A Master first must establish a communication lock with one or more modules during a primary address cycle. Three methods of Primary Addressing are implemented in FASTBUS: Geographical Addressing, Logical Addressing and Broadcast Addressing. In each case the primary address cycle causes one or more slaves to become attached to the Master, and to participate in subsequent data cycles.

Addressing Modes

Primary Addressing

Geographical Addressing of modules refers to the establishment of communication between a Master and a Slave in a particular slot. Because the FASTBUS Segment has a 5-bit slot number hardwired into each slot within the crate (GA00-GA04) each module automatically "knows" its geographical address. When the Enable Geographic bit (EG) is asserted, each module compares its slot address with the five lowest AD lines in order to see if it is being addressed geographically. When the Master also has asserted Address Sync (AS), then the Slave whose slot address is equal to the five lowest AD lines must assert Address AcKnowledge (AK). Once the AS-AK lock has been established, the Master can read or write to the addressed Slave.

Logical Addressing provides the user with the flexibility to relate a module's address to a logical name, i.e., all TDCs could have addresses that begin with 1879, ADCs could have addressing beginning with 1885, etc. In order to implement logical addressing, the module first must be addressed geographically, and then have its logical address register loaded with the logical address. Logical addressing is not mandatory, and does not have to be implemented in a module.

Broadcast Addressing is the method used for communication with more than one Slave. A variety of broadcasts are defined by the FASTBUS specification. Included among the standard broadcasts are "all device" and sparse data broadcasts. The type of broadcast is defined by the Mode Select (MS) lines, the Group Address field, and an 8-bit broadcast function. The standard leaves eight broadcast operations unassigned for special operations to be defined by the user.

Secondary Addressing

Secondary Addressing involves specifying an address to an attached Slave during a data cycle, and is identified by a Mode Select (MS) code. The provisions for secondary addressing allow a FASTBUS module to define up to 232 locations within a module. For example, if a module contains 20,000 words of data, it may not be appropriate to read all words. In that case the module could incorporate secondary addressing in its design, allowing each desired dataword to be separately addressed and read.

Data Cycles

After one or more slaves have been attached (AS-AK lock), data cycles are performed. The secondary address cycle is just one type of data cycle. The Mode Select (MS) code determines which type of data cycle is performed. Single word transfers are normally used for reading status registers. Block transfers and Pipelined transfers are used for bulk data.

It is possible to attach multiple slaves simultaneously via broadcast addressing. In this case a write data cycle transfers the same data to all the attached slaves. Read data cycles are allowed and the backplane does a wire OR of the data read from each of the slaves.

CONTROL AND DATA SPACE

Two address spaces are defined in FASTBUS: Control Space and Data Space. The space being accessed by a given FASTBUS operation is defined by the status of the MS lines at the time of the primary address cycle. Once an address lock is established with a Slave, all data cycles access Control space or Data space, but not both.

Control and Status Registers (CSR) are used for setting operating parameters, checking the operation of a module, etc. CSR0 contains a module identification code. Each module type is assigned a unique 16-bit identifying number which it reports on when CSR0 is addressed and read. Use of all control and status registers is defined in the FASTBUS Standard.

ARCHITECTURE

ATC and GAC modules are required at the ends of every crate Segment and are mounted on the backside of the bus. These modules provide for such functions as bus terminations, arbitration logic, geographical addressing logic, bus arbitration inhibiting and broadcast message system handshake logic.

FASTBUS BLOCK TRANSFERS

To improve the data throughput, most FASTBUS systems use block transfers for moving the experimental data. The block transfer is very efficient at moving data.

Using block transfers in large system requires a FASTBUS master to perform several tasks during the readout of an event. First, slaves with data must be identified. Several broadcast operations are available to assist in this task or this step can be skipped as too time consuming. Next, each slave must be attached (AS-AK lock) in turn and (usually) do single block transfer. If the data block from each slave is small, the overhead of initiating the block transfers can exceed the actual transfer time.

FASTBUS MULTI-MODULE DATA TRANSFERS

The FASTBUS specification describes the multi-module data transfer (MDT) mode. This mode can improve the throughput of block transfers even further. In this specification, several FASTBUS slaves, which are physically adjacent in a FASTBUS crate, can join together in a single block transfer. This relieves FASTBUS master from the chore of addressing each slave individually.

Before the MDT mode can be used, the FASTBUS master must configure the slaves with bits in the Control Space Register 0. The slaves must each be configured as the first, middle, or last slave in the group. This configuration is required only once. After configuration, the master addresses the first slave in the group and reads all the data from all the slaves in a single block transfer. The slaves pass tokens to each other to achieve the appearance, to the FASTBUS master, of a single module.

The MDT mode is not a required part of the FASTBUS specification. Check the particular FASTBUS slave specifications before attempting to use this mode.

SOFTWARE

A document is available that defines standard routines for use with FASTBUS. It has been developed by the Software Working Group of the NIM Committee. It can be obtained from: National Technical Information Service, U.S. Department of Commerce, Springfield, VA 22161, Request Document: DOE/ER-0367.

FASTBUS Module Connector Pin-Outs

Crate and Cable Segment Signal and Power Lines