FEATURES
High Speed DMA Data Transfer (to 900 KBytes Per Second)
Includes CAMAC Support Software for Most Popular Programming
Languages
TurnKey Menu Driven Data Acquisition System Software Available for
Set-up, Control, Data Transfer, Display and Analysis
Built-in Dataway Display Simplifies System Maintenance and Program
Development
Compatible with Microcomputer Type Buses.
DESCRIPTION
Either a Model 6001 or 6002 CAMAC Crate Controller together with a
Model PC004 plug-in card for an IBM PC/XT/AT compatible personal
computer (including 80386 based machines) provides a high speed DMA
interface between the computer and the instrument modules installed
in the CAMAC crate. Support software for most popular programming
languages is included. Higher level menu driven data acquisition
system support software is available separately.
The Model 6001 and 6002 are combined CAMAC Crate Controllers and Dataway Display Modules. This saves one CAMAC slot normally necessary for the dataway display function, a very useful tool in debugging data acquisition software. The status of the last CAMAC cycle executed is displayed on the front panel LED's.
The module accepts data and commands from the computer, executes the CAMAC commands and transfers data back to the computer. Direct memory access (DMA) data transfers of up to 900 kbytes per second are supported.
The Model 6002, in addition to being able to function as a standard crate controller, can also be used as an Auxiliary Crate Controller (ACC). For example, two Model 6002s can be installed in a single crate at the same time to allow two different IBM compatible computers access to the instrumentation modules. Similarly, a Model 6002 can be installed along with another model Auxiliary Crate Controller to simultaneously interface a CAMAC crate to both an IBM compatible and to another type host computer such as a DEC VAX or an IEEE-488 (GPIB) controller.
The Model PC004 is an IBM PC plug-in card that interfaces to either a 6001 or 6002. An interconnect cable and support software (Model 9100) for programmed I/0 and DMA transfers are included with the PC004. A single PC004 provides connections to up to four 6001/6002s (i.e. up to four crates). Jumpers can be installed to permit LAM interrupt servicing.
The programming languages supported are:
Microsoft Basic
Borland Turbo Pascal
ASYST
Microsoft Fortran
Borland Turbo C
IBM Professional Fortran
Microsoft Pascal
Microsoft C
TECHNICAL SPECIFICATIONS: FRONT PANEL LED Indicators: Display the result of the last CAMAC command executed. LAM lights, which are priority en- coded, are on whenever a module generates a LAM. Clear Display: Push button which clears the display. Clear Dataway: Generates a CAMAC clear. I/0: 40 pin connector which interfaces the module to the host computer. 6002 ONLY: CC LED: When lit, indicates that 6002 is in main Crate Controller mode and must be installed in two rightmost slots. ON LINE/OFFLINE SWITCH: Allows 6002 to be set into "Off line" mode in which it will not issue CAMAC cycles. REQUEST Connector: ACC Request line. LEMO con- nector. GRANT OUT Connector: ACC Grant Out Line. LEMO Connector GRANT IN Connector: ACC Grant In Wire. LEMO Connector. NOTE: For proper Auxiliary Crate Controller operation, the highest-priority crate controller should have its Re- quest connected to its Grant In. A lower-priority crate controller should have its Grant In connected to the Grant Out of the crate controller with the next highest priority. Operation of the 6002 without other crate con- trollers requires that it be configured as a Main Crate Controller and that its Request be connected to its Grant In. AUXILIARY CONTROL BUS: The 6002 has a CAMAC standard auxiliary control bus connector on the rear panel. IEEE Std. #675 is the specification for this bus. POWER REQUIREMENTS +6V, 1.3A. PACKAGING #2 width CAMAC module 221 mm H, 34 mm W, 292 mm D (8.7" x 1.4" x 11.5") Depth front to rear panel. Rear connector 13 mm (0.5"). In conformance with the CAMAC standard for RF shielded instrumentation modules (IEEE standard 583, European Esone Report # ERR4100e). The following are trademarks or registered trademarks of their respective companies: IBM PC/XT/AT & IBM Professional Fortran of International Business Machines Corporation. DEC VAX of Digital Equipment Corporation. Microsoft of Microsoft Corporation, Turbo C and Turbo Pascal of Borland International. Inc. ASYST of Asyst Software Technologies, Inc. CAMAC COMMANDS LAMs: The CAMAC LAMs (Look at Me) are priority en- coded with station 1 as highest priority and 23 as lowest. A flag bit is generated in the 6001/6002 whenever a LAM signal is present within the crate. 0, X: The Q and X bits reflect the status of the CAMAC X and Q lines during the last CAMAC cycle. Z, C: A CAMAC Initialize or Clear command may be generated by loading the appropriate bit of register A6 and initiating a CAMAC cycle. These bits are reset after the CAMAC cycle is completed. I: Sets the CAMAC inhibit line. Data read or written is passed over a byte-wide, bidirec- tional bus controlled by four address lines and six con- trol lines. The four address lines which select internal registers for reading/writing data are: Addreses Address Lines Function BAS BA4 BA2 BA1 AO L L L L Stores CAMAC WH BYTE F17-W24) Data A1 L L L H Stores CAMAC WM BYTE (W9-W16) Data A2 L L H L Stores CAMAC WL BYTE (W1-WS) Data A3 L L H H Stores CAMAC A Subaddress Data (0-15) A4 L H L L Stores CAMAC F Function Data (0-31) A5 L H L H Stores CAMAC N Station Data (0-23) A6 L H H L Stores CAMAC Z,C,I, and Aux Inhibit Hold Control Data A7 L H H H Starts a CAMAC cycle A8 H L L L Reads CAMAC Q,X, and encoded LAM A9 H L L H Reade RH BYTE (R17-R24) Data A10 H L H L Reads RM BYTE (R9-R16) Data A11 H L H H Reads RL BYTE (R1-RS) Data A12 H H L L Reads Statue Register (LSB-CAMAC Cycle Complete, LSB+1-ACL State, LSB+2-High A15 H H H H DMA control and statue register (PC004) for on line The six control lines are: BDS: Master enable which must be low to address the unit. BR/W: Controls data flow on the bi-directional bus-high to read, low when addressing registers 0-6 and high for registers 8-11. BQ3: Timing signal used when writing data into the unit. CC: Active low TTL pulse initiates CAMAC Cycle. L: Active low TTL when LAM is present. Q: 0 status of last CAMAC cycle.