GENERAL DESCRIPTION
The JY411 is designed to be powered from the same switched AC source
as the processor. BZ is always issued on power-up. A rear panel
switch allows BZ to be enabled/inhibited during other Unibus INIT
cycles. In either switch position, BZ can be issued via the
Control/Status Register.
The JY411 occupies eight sequential PDP11 word addresses, with the lowest six used to control and monitor JY411 functions; the other two are unused and reserved. The lowest JY411 address must have 0 for its low-order octade. These addresses may be in the range 764000`8/777777`8; PDP11 convention constrains this range to 764000`8/ 767777`8.
Relative Address Assignment: (Standard first address in 766000`8)
0 Control/Status Register
2 Data Register
4 Memory Address Register
6 Crate Select/Word Count Register
10 Instruction Register
12 Extended Word Count/Control Register
The JY411 may generate two levels of Bus requests; NPR-DMA transfers and BR7:4 (hardware-selectable), which may generate Interrupt Requests. DMA transfers are to or from the address specified by the JY411 Memory Address Register; Interrupt Re- quests are to two addresses (hardware-selectable). Standard assignments are BD trap at 270 and Task Completion trap at 274. Standard Priority is BR4