LeCroy 1810 Calibration and Trigger Module

FASTBUS Model 1810 Calibration And Trigger Module

The Model 1810 is a FASTBUS module designed to accommodate the calibration and trigger functions of the System 1800 Data Acquisition Crate. The Calibration And Trigger module, CAT, may be placed in any slot of a standard FASTBUS crate. It receives and distributes the strobes required to operate the Data Acquisition Modules. The required clock signals and calibration pulses are also distributed from the CAT. The FASTBUS backplane is used for all of these operations.

The CAT may be downloaded with control words used to set the operating conditions for the DAM'S, i.e., clock frequencies for the TDC and ICA modules. The CAT also accepts control words to set up the calibra- tion pulses and levels for the DAM'S. The charge to be applied to the ADC channels is 12-bit program- mable. The times and pulse widths may be separately programmed for TDC channels. A second pulse may be enabled to test the compacting circuitry of the TDC. The ADC amplitude word and TDC timing pulse also program the calibration test pulser in the ICA.

The control words are loaded into control Space Register and DATA space within the CAT. The write opera- tions follow standard FASTBUS protocol with the Model 1810 acting as a SLAVE. During the write (and readback) operations, a yellow LED is illuminated on the front panel of the CAT.

To enable the CAT to process trigger strobes requires that the Acquisition Mode (AM) be established. The Crate Master, usually a Model 1821, gains mastership of the Segment from the Arbitration Timing Controller (ATC) and generates an AM broadcast. The CAT recognizes this operation, and 1800 DAM's within the crate are initialized for data acquisition. The CAT then uses the segment to transmit its signals to the DAM'S. The TR lines are used in order not to compromise use of the crate during the AM.

The event time is defined as the earliest of the three system strobes (ADC Gate, TDC Common Stop and ICA Common Stop). The Measure Pause Intervals begins at the event time and lasts for 0-63 usec. It is FASTBUS programmable. A-Master may then begin read out of the DAM'S. A Fast Clear pulse received at the CAT during the MPI restarts TDC and ICA clocks and applies a Fast Clear pulse to the ADC modules.

At the end of the MPI, the CAT provides the trailing edge of the Common Stop pulse. This action is used by the DAM's to initiate data conversion.

SPECIFICATIONS

INPUTS

A Gate In:*

Defines the integrating time for the ADC's. Distributed to 1882,1885 modules via the FASTBUS segment. Duration 50-2000 nsec. Begins the MPI.

T Common Stop:*

Minimum width 50 nsec. Stops the oscillator signals used to clock the pipeline TDC's. Begins the MPI.

I Common Stop:*

Minimum width 50 nsec. Stops the oscillator signals used to clock the [CAs. Begins the MPI.

ATI Fast Clear:*

Minimum width 50 nsec. Distributes fast clear signal to ADC modules, restarts the TDC and ICA oscillators and terminates the MPI.

TI Personality Card Strobe:*

Minimum width 50 nsec. Supplies a pulse to the personality cards to define the event time. Not used by the DAM'a.

TI Test In:*

Minimum width 50 nsec. Applies timing pulses to the TDC and ICA DAM's. Used in conjunction with the Common Stop inputs.

OUTPUTS

AI Level:

Output via a Lemo connector. Supplies 0 to + 10 V DC level used to program the ADC and ICA pulsers. Output impedance 1 K ohm.

MPI In:

Bidirectional port used to synchronize the MPI's in all crates. Provided via two identical

MPI Out:

Lemo connectors. Bidirectional current sink: output - 28 mA at - 1.4 V; input 50 ohm, - 1.4 V to enable. When daisy chained, the duration of the MPI at all CAT's in the daisy chain is equal to the duration of the longest MPI in the chain.

Busy Mode:

A NIM false level indicates that the crate is in the AM. NIM True indicates a trigger has been received.

DATA ACQUISITION CONTROL

I/T Osc Frequency:

A 7-bit programmable divide down factor covering a factor of 2 (Data Space).

CALIBRATION CONTROL

ICA:

TBA.

TDC:

Programs the time of the trailing edge of a time pulse, and the time of the stop pulse (Data space). Also enables and disables a second pulse approximately midway be- tween pulse 1 and the Common Stop (CSR Space).

ADC:

A 12-bit amplitude word. Sets the amount of charge injected into each ADC when the test feature is enabled (Data Space).

GENERAL

Power Requirements:

50 mA at + 15 V
1.0A at +5V
4.0 A at - 2 V
6.5 A at - 5.2 V
1.00 mA at - 15 V

Packaging:

Single width FASTBUS module in conformance with FASTBUS specification dated December, 1983.

FASTBUS CONTROL

Implemented Addressing Modes:

Geographical, Secondary, Broadcast

Implemented Broadcast Functions:

Code

Significance

Comments

(OD)h**

All device scan

The 1810 asserts its "T pin" on following read cycles.

(8D)h

AM

Begins acquisition mode.

Slave Status Response to Data Cycles:

SS

Significance

0

Valid action

6

Error, data rejected

CONTROL FUNCTIONS IMPLEMENTED

Module Identification Code:

(Read only) (1038)h

Test Pulse:

Disable, enable one pulse, enable double pulse

Cal Trigger:

NIM pulse signifying that the crate has entered the acquisition mode-typically 85 nsec.

*Two inputs, one bridged high impedance Lemo pair accepting NIM inputs, and one 110 Q impedance two-pin header accepting differential ECL inputs.
**An h subscript denotes a hexadecimal number, i.e., base 16.

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INPUTS
A Gate In:*	Defines the integrating time for the ADC's. Distributed to 1882,1885 modules via the FASTBUS segment. Duration 50-2000 nsec. Begins the MPI.
T Common Stop:*	Minimum width 50 nsec. Stops the oscillator signals used to clock the pipeline TDC's. Begins the MPI.
I Common Stop:*	Minimum width 50 nsec. Stops the oscillator signals used to clock the [CAs. Begins the MPI.
ATI Fast Clear:*	Minimum width 50 nsec. Distributes fast clear signal to ADC modules, restarts the TDC and ICA oscillators and terminates the MPI.
TI Personality Card Strobe:*	Minimum width 50 nsec. Supplies a pulse to the personality cards to define the event time. Not used by the DAM'a.
TI Test In:*	Minimum width 50 nsec. Applies timing pulses to the TDC and ICA DAM's. Used in conjunction with the Common Stop inputs.
OUTPUTS
AI Level:	Output via a Lemo connector. Supplies 0 to + 10 V DC level used to program the ADC and ICA pulsers. Output impedance 1 K ohm.
MPI In:	Bidirectional port used to synchronize the MPI's in all crates. Provided via two identical
MPI Out:	Lemo connectors. Bidirectional current sink: output - 28 mA at - 1.4 V; input 50 ohm, - 1.4 V to enable. When daisy chained, the duration of the MPI at all CAT's in the daisy chain is equal to the duration of the longest MPI in the chain.
Busy Mode:	A NIM false level indicates that the crate is in the AM. NIM True indicates a trigger has been received.
DATA ACQUISITION CONTROL
I/T Osc Frequency:	A 7-bit programmable divide down factor covering a factor of 2 (Data Space).
CALIBRATION CONTROL
ICA:	TBA.
TDC:	Programs the time of the trailing edge of a time pulse, and the time of the stop pulse (Data space). Also enables and disables a second pulse approximately midway be- tween pulse 1 and the Common Stop (CSR Space).
ADC:	A 12-bit amplitude word. Sets the amount of charge injected into each ADC when the test feature is enabled (Data Space).
GENERAL
Power Requirements:	50 mA at + 15 V 1.0A at +5V 4.0 A at - 2 V 6.5 A at - 5.2 V 1.00 mA at - 15 V
Packaging:	Single width FASTBUS module in conformance with FASTBUS specification dated December, 1983.
FASTBUS CONTROL
Implemented Addressing Modes:	Geographical, Secondary, Broadcast
Implemented Broadcast Functions:	Code	Significance	Comments
	(OD)h**	All device scan	The 1810 asserts its "T pin" on following read cycles.
	(8D)h	AM	Begins acquisition mode.
Slave Status Response to Data Cycles:	SS	Significance
	0	Valid action
	6	Error, data rejected
CONTROL FUNCTIONS IMPLEMENTED
Module Identification Code:	(Read only) (1038)h
Test Pulse:	Disable, enable one pulse, enable double pulse
Cal Trigger:	NIM pulse signifying that the crate has entered the acquisition mode-typically 85 nsec.
Two inputs, one bridged high impedance Lemo pair accepting NIM inputs, and one 110 Q impedance two-pin header accepting differential ECL inputs. *An h subscript denotes a hexadecimal number, i.e., base 16.