GENERAL DESCRIPTION

The LRS Model 2248 Multi-ADC contains eight complete eight-bit analog-to-digital converters in o single-width CAMAC module. These ADC's are specifically intended for digitization of photomultiplier pulses and similar fast transient signals. They are especially well suited to use in large systems because of their low cost, compactness, simplicity of operation, and system- oriented control and test features. They accept and digitize nanosecond pulses directly without need for prior stretching or preshaping of any kind. Input polarity is negative for photomultiplier anode pulses; however, positive pulses or negative pulses with positive undershoot con also be handled linearly. Inputs are direct-coupled for freedom from rate effects and highly stable with time and temperature. A common linear gate establishes the time window during which the analog inputs ore active. This input is operated by standard NIM level signals from 10 to 200 nanoseconds in duration.

The Model 2248 offers o number of convenient and flexible features. A unique conversion mode control provides the choice of two linear modes with sensitivities of 0.25 pC/count or 1 .0 pC/count, or three bilinear modes. (See curve.) The bilinear modes provide an effective increase in the dynamic range as compared with simple linear conversion by digitizing the lower portion of the output range at 0.25 pc/count and switching at one of three selected points to 1 .0 pC/count. A simple CAMAC-controlled internal test checks all ADC's simultaneously, from input to output, providing a convenient and practical monitor of proper system operation with minimal interference with data -taking. Other flexible features include provisions for connecting two status commands (Active, end of conversion Flog) to CAMAC patch points, readout of two adjacent modules in the form of eight 16-bit words, and suppression of Q response for modules with less than a preselected number of counts in all of the eight channels.

The Model 2248 represents a very substantial advance in fast pulse ADC capability. In high energy physics, it will permit the use of ADC's for both measurement and monitoring purposes to an extent not previously practical, since for the first time the ADC cost becomes low compared to the existing experimental per-channel investment in the counter assembly and associated electronics and hardware.

SPECIFICATIONS

 Analog Inputs:   Eight; Lemo-type connectors; charge sensitive
     (current integrating); direct-coupled, quiescently
     at approximately +3 mV; 50 Ohm impedance; linear
     range normally 0 to -1 V; pedestal adjust allows
     offsetting linear range continuously by up to +250 mV
     (+250 mV to -750 mv); protected to +/-50 volts against
     1 usec. transients.

 Bilinear Mode:   Five-position switch (accessed from side of module)
     provides choice of two linear modes with sensitivi-
     ties of 0.25 pC/cou nt or 1 .0 pC/count, or three
     bilinear modes, beginning with 0.25 pC/count
     sensitivity and switching at selected point (8, 16,
     or 32 pC) to 1 .0 pC/count sensitivity. (See curve).
     Switching is digital; ratio is precisely 1:4.

 Full-Scale Ranges:  From 64 pC to 256 pC (3.2 to 12.8 volt-ns),
     dependent upon Bilinear Mode position.

 Full-Scale Uniformity:  +/-5%.

 Linearity:   Within +/-3 counts of the best straight line.

 ADC Resolution:  8 bits actual (0.40/o); 10-bit equivalent (0.1%) in
     bilinear mode.

 Long Term Stability:  Better than 0.5% of reading +/-0.5 pC/week.

 Temperature Coefficient: -0.05%/'C typical.

 ADC Isolation:   A 5-volt, 20 ns overload pulse in any one ADC
     disturbs data in any other ADC by no more than
     0.25 pC.

 Gate Input:   One gate common to all ADC'S; 50 Ohm impedance;
     -750 mV or greater enables; minimum duration,
     10 ns; maximum recommended duration, 200 ns.
     (Actual limit approximately 3 microseconds with
     reduced accuracy); effective opening and closing
     times, 2 ns.


 Residual Pedestal:  Typically 1 + 0.03t picocoulombs (where t = gate
    duration in nanoseconds) with 50 Ohm reverse
    termination.

 Pedestal Adjust:  Single front-panel 15-turn potentiometer for all
    eight ADC's. Injects a constant DC current adjust-
    able from 0 to 5 mA (0 to +250 mV equivalent if
    referred to input) into all ADC's without disturbing
    actual inputs. Resulting offset (pedestal) is propor-
    tional to gate duration.

 Digitizing Time:  From 25 usec. at 64 pC full scale to 1 00 usec. at
    256 pC full scale.

 Readout Time:   Readout may proceed at the fastest rate permitted by
    the CAMAC standard after digitization is complete.
    May be shortened by Q response suppression of
    empty modules.

 Readout Control:  Channel 0 is ready for readout when Flag signal
    appears. S2 timing pulse readies next channel in
    sequence (Subaddress A + 1). Refer to ESONE
    Committee Report EUR4100e and EUR4600e for
    additional timing details, voltages, logic levels,
    impedances, and other standards.

 Data:    The proper CAMAC function and address command
    normally gates the 8 binary bits onto the Rl to R8
    (20 to 27 ) Dataway bus lines.

 Overflow Indication:  A full-scale count (255 in decimal or 11111111 in
    binary) constitutes an overflow or "off-scale" flag.

 Readout Compacting:  Two patch point jumpers per pair of modules on
    rear of CAMAC crate allow automatic cascading
    of two units, so that when reading the first module
    data to normal R1 to R8 Dataway buses, the second
    module simultaneously reads data to R9 to R1 6 Dataway
    buses. ("N" representing the first module also
   addresses the second module, but "N" of second
   module is ignored.) Optional jumper to patch
   point-bus provides ability to disable compaction
   by bus control.

Active Signal:  Open collector TTL clamp to ground from gate
   closing time until unit is cleared. Solder option
   allows connecting Active output to CAMAC
   patch point. (Optional jumper allows inversion.)

Flog Signal:  Open collector TTL normally clamped to ground
   except for time duration from end of conversion
   until unit is cleared. Solder option allows
   connecting Flog output to CAMAC patch point.
   (Optional jumper allows inversion.) Flag con be
   used as a LAM.

CAMAC Commands: Z or C: ADC's are cleared by the CAMAC "Clear"
   or "Initialize" command; require S2.

   I:Gate input is inhibited during CAMAC "Inhibit"
   commands. Inhibit can be manually disabled by
   front-panel switch.

   Q: A Q=l response is generated in recognition of
   an F(O), F(2), F(9), or F(25) function for a valid "N"
   and "A", but there will be no response (Q=0)
   under any other condition. The Q response is sup-
   pressed during conversion time. It can also be sup-
   pressed for empty modules. (See Q response sup-
   pression .)
   X: An X=1 (Command Accepted) response is gener-
   ated when a valid F, N, and A command is generated.
   It is suppressed during the conversion time.