LeCroy 2280 ADC system Processor

SPECIFICATIONS CAMAC Model 2280 SYSTEM PROCESSOR

FRONT PANEL INPUTS (LEMO TYPE CONNECTORS) Gate: 50 Ohm impedance. - 600 mV or greater enables. Distributed to ADC modules via ASB. Gates received after start of conversion are locked out. Use of gate disabled output recommended to avoid partial gating during enabling or fast clearing. 50 nsec minimum width. Clear: Common to all ADC'S. 50 Ohm impedance. - 600 mV or greater enables. 50 nsec minimum width. (See individual ADC specifica- tions for settling time.) Distributed to ADC modules via the ASB. Test Level: During the test cycle a signal proportional to the applied voltage (internal high impedance connection to + 8 V) will be present at all ADC inputs about 20 nsec after gate opening. Distributed via ASB. Grant In: Requires TTL clamp to ground(for Type A2 CAMAC controller). FRONT PANEL LED's (internally stretched to 1 msec minimum) N Light: Indicates when unit is being addressed. Busy Light: Indicates when the Model 2280 has seized control of the CAMAC dataway. FRONT PANEL OUTPUTS (LEMO TYPE CONNECTORS) Test Trigger: Provides NIM level signal of usec duration to trigger external gate logic when processor receives F(25)-A(l) Gate Disabled: Provides TTL clamp to ground when ever process or is not ready to receive a gate. Conversion: Provides TTL clamp to ground from trailing edge of gate until end of conversion. Data Ready: Provides TTL clamp to ground from end of conversion, if data was stored in memory, until last word is read or unit is cleared. Request: Provides TTL clamp to ground (for Type A2 CAMAC controller). Grant Out: Provides TTL clamp to ground (for Type A2 CAMAC controller). SYSTEM OPERATION Conversion (Scaling & Data Transfer): The System must first be enabled by an F(26)-A(4). This com- mands the processor to take control of the CAMAC crate, which then causes the CAMAC BUSY to be clamped, resets the ADCS, and permits acceptance of an external gate to the processor (which is transmitted to the ADC's via the ASB). After a "wait" time (to allow for a fast clear) the processor supplies the scaler clock train required by the ADC's followed by readout of each module. Data of groups of twelve ADC channels are simultaneously shifted out serially to the processor via dataway buses R13 - R24. The data are converted to parallel form, preprocessed (see Pedestal Subtraction and Data Compres- sion), and stored in the data memory. When all data are processed, the processor is automatically disabled, the BUSY line is released, and a LAM is generated. Pedestal Subtraction: The processor contains a 1024-word by 12-bit pedestal memory. This memory is loaded from the dataway by sequentially writing up to 1008 pedestal values using F(16)-A(O). If pedestal subtraction has been selected via coding of the F(16)-A(3) control word, incoming ADC data is automatically corrected before being loaded into the processor's memory.

Specifications

Data Compression:

Data compression is performed by analyzing the data according to a user-entered digital threshold and cluster edge size. All data >= threshold are stored in the data memory plus up to 15 channels of data on either edge of the region over threshold. Cluster blocks, which can be any length, are preceded in memory by the address of the first word in the cluster.

Reading of Actual Pedestal:

The control word register should be formulated so that Data Compression is not enabled, Pedestal Subtraction is not enabled, Data Transfer is enabled, and the Test Mode is not enabled. With no signal being applied to the analog inputs, a data-taking sequence, which can be initiated with F(25-A(l), will cause actual pedestal values to be stored in the data memory. Readout is accomplished via F(2)-A(O).

Reading of Stored Pedestal:

The control word register should specify that Data Compression is not enabled, Pedestal Subtraction is enabled, and Data Transfer is not enabled. A data-taking sequence will cause stored pedestal values to be stored in the data memory. Readout is accomplished via F(2)-A(O). The data will be a 16-bit two's complement of the actual pedestal value. This would be read by many 16-bit computers as "Pedestal"

Clearing:

Upon being enabled, the processor always fully clears the system to prepare it for a data-taking cycle.

CAMAC CONTROLS AND READOUT OF 2280 PROCESSOR

CAMAC Readout:

Readout may proceed at the fastest rate permitted by the CAMAC standard after scaling and transfer are complete. (See CAMAC Function Codes.)

CAMAC Data:

The proper CAMAC function gates 16-bit data or status words into the CAMAC dataway. ADC data is presented with a starting address followed by consecutive data words gated onto the R1 to R15 bus lines. Overflow is indicated by all ADC bits being set high (4095 for a 12-bit ADC). R16 is a sign bit (1 = neg. data, as a result of pedestal subtraction from noisy data) and R15 is address f lag (O = address flag if R16 = 1).

CAMAC Commands:

C:

Clear System; initializes data memory address register, word count register, pedestal memory address register, and LAM. Also issues analog (fast) clear to ADC modules. If the processor is enabled, a digital (slow) reset is also applied to the ADC modules.

Z:

Initialize system: same as C except also disables processor and LAM. Will not issue a digital reset to ADC modules.

I:

Gate Input of controller is inhibited during CAMAC "inhibit" command. (Connected via a jumper.)

Q:

A Q = 1 response is generated for all valid F(O) or F(2) commands (if data is contained in the data memory), all valid F(l) and F(16) commands, an F(27)-A(O) (if LAM is set independent of LAM mask), or an F(8)-A(O) if LAM is set and enabled.

L:

A Look-At-Me signal (when enabled) is generated as soon as the data of all ADC channels in the crate have been processed. LAM is cleared as soon as the first data word is read with F(2)-A(O). User jumper option allows LAM to remain true until all valid data words have been read. (Extended LAM).

CAMAC Function Codes:

F(O)-A(O):

Read Data without advancing Address Register.

F(2)-A(O):

Read Data and advance Address Register; clears LAM.

F(2)-A(l):

Read Cluster Edge Size.

F(2)-A(2):

Read Digital Threshold.

F(2)-A(3):

Read Data Set Size (# of address and data words remaining in memory).

F(8)-A(O):

Test L; Q = 1 is generated if LAM is set and is not disabled by LAM mask.

F(9)-A(O):

Clear System: same as C above.

F(10)-A(O):

Clear LAM. Inoperative if extended LAM option is selected.

F(16)-A(O):

Write sequentially = < 1008 12-bit pedestal values. Pedestal values are written in reverse order to data readout, Write "minus pedestal" in two's complement form. (Must be preceded by C, Z or F(9)-A(O) to initialize pedestal address register.)

F(16)-A(l):

Write Cluster Size; 4-bit word.

F(16)-A(2):

Write Digital Threshold; 16-bit word.

F(16)-A(3):

Write Control Word; 5-bit selects control option.

W5 = Enable Positive Pedestal Mode.
W4 = Enable Calibration Input.
W3 = Enable Data Transfer (ADC's to processor).
W2 = Enable Pedestal Subtraction.
W1 = Enable Data Compression.

F(24)-A(O):

Disable L (mask LAM).

F(25)-A(l):

Enable Processor; generates 1 usec test trigger pulse; independent of "Enable Calibra- tion Input" control word option.

F(26)-A(O):

Enable L (mask LAM).

F(26)-A(4):

Enable Processor for data taking.

For proper system operation it is imperative that while a conversion is in progress no activity caused by the crate controller occurs on the dataway.

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Data Compression:	Data compression is performed by analyzing the data according to a user-entered digital threshold and cluster edge size. All data >= threshold are stored in the data memory plus up to 15 channels of data on either edge of the region over threshold. Cluster blocks, which can be any length, are preceded in memory by the address of the first word in the cluster.
Reading of Actual Pedestal:	The control word register should be formulated so that Data Compression is not enabled, Pedestal Subtraction is not enabled, Data Transfer is enabled, and the Test Mode is not enabled. With no signal being applied to the analog inputs, a data-taking sequence, which can be initiated with F(25-A(l), will cause actual pedestal values to be stored in the data memory. Readout is accomplished via F(2)-A(O).
Reading of Stored Pedestal:	The control word register should specify that Data Compression is not enabled, Pedestal Subtraction is enabled, and Data Transfer is not enabled. A data-taking sequence will cause stored pedestal values to be stored in the data memory. Readout is accomplished via F(2)-A(O). The data will be a 16-bit two's complement of the actual pedestal value. This would be read by many 16-bit computers as "Pedestal"
Clearing:	Upon being enabled, the processor always fully clears the system to prepare it for a data-taking cycle.
CAMAC CONTROLS AND READOUT OF 2280 PROCESSOR
CAMAC Readout:	Readout may proceed at the fastest rate permitted by the CAMAC standard after scaling and transfer are complete. (See CAMAC Function Codes.)
CAMAC Data:	The proper CAMAC function gates 16-bit data or status words into the CAMAC dataway. ADC data is presented with a starting address followed by consecutive data words gated onto the R1 to R15 bus lines. Overflow is indicated by all ADC bits being set high (4095 for a 12-bit ADC). R16 is a sign bit (1 = neg. data, as a result of pedestal subtraction from noisy data) and R15 is address f lag (O = address flag if R16 = 1).
CAMAC Commands:
C:	Clear System; initializes data memory address register, word count register, pedestal memory address register, and LAM. Also issues analog (fast) clear to ADC modules. If the processor is enabled, a digital (slow) reset is also applied to the ADC modules.
Z:	Initialize system: same as C except also disables processor and LAM. Will not issue a digital reset to ADC modules.
I:	Gate Input of controller is inhibited during CAMAC "inhibit" command. (Connected via a jumper.)
Q:	A Q = 1 response is generated for all valid F(O) or F(2) commands (if data is contained in the data memory), all valid F(l) and F(16) commands, an F(27)-A(O) (if LAM is set independent of LAM mask), or an F(8)-A(O) if LAM is set and enabled.
L:	A Look-At-Me signal (when enabled) is generated as soon as the data of all ADC channels in the crate have been processed. LAM is cleared as soon as the first data word is read with F(2)-A(O). User jumper option allows LAM to remain true until all valid data words have been read. (Extended LAM).
CAMAC Function Codes:
F(O)-A(O):	Read Data without advancing Address Register.
F(2)-A(O):	Read Data and advance Address Register; clears LAM.
F(2)-A(l):	Read Cluster Edge Size.
F(2)-A(2):	Read Digital Threshold.
F(2)-A(3):	Read Data Set Size (# of address and data words remaining in memory).
F(8)-A(O):	Test L; Q = 1 is generated if LAM is set and is not disabled by LAM mask.
F(9)-A(O):	Clear System: same as C above.
F(10)-A(O):	Clear LAM. Inoperative if extended LAM option is selected.
F(16)-A(O):	Write sequentially = < 1008 12-bit pedestal values. Pedestal values are written in reverse order to data readout, Write "minus pedestal" in two's complement form. (Must be preceded by C, Z or F(9)-A(O) to initialize pedestal address register.)
F(16)-A(l):	Write Cluster Size; 4-bit word.
F(16)-A(2):	Write Digital Threshold; 16-bit word.
F(16)-A(3):	Write Control Word; 5-bit selects control option. W5 = Enable Positive Pedestal Mode. W4 = Enable Calibration Input. W3 = Enable Data Transfer (ADC's to processor). W2 = Enable Pedestal Subtraction. W1 = Enable Data Compression.
F(24)-A(O):	Disable L (mask LAM).
F(25)-A(l):	Enable Processor; generates 1 usec test trigger pulse; independent of "Enable Calibra- tion Input" control word option.
F(26)-A(O):	Enable L (mask LAM).
F(26)-A(4):	Enable Processor for data taking.
For proper system operation it is imperative that while a conversion is in progress no activity caused by the crate controller occurs on the dataway.