|
Input Sensing |
Charge (current integrating). |
|
ADC Resolution |
12 bits. |
|
Full Scale |
- 400 pC +/- 10%. |
|
Common Mode Properties |
For +/- 100 mV, CMRR of 40 dB at 60 Hz, 30 dB at 1 kHz for source impedance > 50 Ohm. |
|
Gain Variations |
+/- 10% deviation from mean. |
|
Input Impedance |
50 Ohm +/- 5%; 0 to - 60 mA. |
|
Input Protection |
+/- 25 V for 1 usec transients. |
|
Input Limitations |
Maximum voltage for linear response, - 1.5 V. For 3 V maximum input linearity is degraded to typically +/- (1 % of reading + 0.5 pC). |
|
Integral Linearity |
Typically +/-(0.l% of reading of +0.25 pC); worst case +/- (0.25% of reading +0.5 pC) for signals of slew rate =< 2 mA/nsec. For signals of slew rate 4 mA/nsec linearity is degraded to typically +/- (1% of reading + 0.5 pC). |
|
Differential Linearity |
Typically 25%. |
|
Residual Pedestal |
Typically 50 pC(subtracted from data by processor) for a gate width of 200 nsec and a high source impedance. |
|
Pedestal-Gate Width Coefficient |
< +/- 50 fC/nsec for gate widths >100 nsec. |
|
Temperature Coefficient |
Typically +/- (0.1% of reading + 0.00025 pC T)/'C where At = gate width in nsec. |
|
Long-Term Stability |
+/- (0.25% of reading + 0.5 pc)/week at constant temperature and voltage. |
|
Conversion Time |
200 usec nominal + 22 usec per ADC module. |
|
Operating Temperature |
0 to 40'C. |
|
ADC Isolation |
> 60 dB, including the effects of one input connector. |
|
Gate Input |
One per module, rear panel input driven from nonregenerative driver (via ASB) in 2280 System Processor module. |
|
Gate Width |
50 nsec to 1500 nsec. In operation with wide gates, ADC conversion gain depends on pulse position in ADC gate time. This dependence is typically 0.6%/usec. |
|
Gate Timing |
The gate input to the 2280 System Process or must precede the analog inputs by >=50 nsec. |
|
Fast Clear |
May be executed any time. Settles from full scale to within 1 count (100 fC) in < 2 usec. |
|
Digital Clear |
A digital clear is automatically generated by a fast clear >=6 usec after the gate. Requires 3 usec to settle. |
|
Test Feature |
Exercised by 2280 System Processor. All channels have a test pulse applied. The amplitude of the pulse is proportional to a DC level applied to the Test Input (0 to + 8 V), typically 47 pC/volt. Matching to nominal of the test pulse is +/- 10%. Requires a gate width of => 300 nsec. |
|
Analog Outputs |
Current outputs proportional to input (~0.5 mA/mA) available at each hybrid for summing by user. Risetime > 25 nsec, 10-90%. Three output buffers on rear panel allow option for additional current summing. Gate feed through is typically 80 mV (into 50 ohms) for 16 channels, recovered in 80 nsec. |
|
Readout and Control |
Requires one Model 2280/85 Processor per CAMAC crate. |
|
Packaging |
No. 1 RF-shielded CAMAC module conforming to ESONE Report EUR 4100 and IEEE Standard 583. |
|
Power Requirement |
770 mA at + 6 V 160 mA at + 24 V (plus 1.5 times average input current) 325 mA at - 6 V Oat -24V |
|
Special Options |
15-bit operation and variable gain. Specially modified System Processor (Model 2280/85/15) allows 15-bit conversion. Side panel accessed jumpers allow external voltage program- ming of ADC gain over the range 10 to 30 counts/pC. Voltage range + 6.3 V to 2.1 V. The model 2285A/15 is tested at both 12- and 15-bit operation and at both 10 and 30 fC per count. Model 2285A specifications include only 12-bit 10 count/pC gain operation. CAUTION: Sensitivity should be selected to give a full scale of 1000 pC or less. |
|
Analog Input Cable |
LeCroy Model DK6/50-Length. 4 per module. Includes AMP 226298-6 six-pair ribbon coaxial cable with termination by AMP 226651-6 connectors at both ends, plus one AMP 87606-2 bulkhead-mounting 6-pair connector |