LeCroy 2340A Discriminator Coincidence Register

The LRS Model 2340A Discriminator Coincidence Register ("pattern unit") offers high-performance discriminator and fast storage functions in computer-compatible CAMAC standard packaging. The integrated circuit design affords the highest density packaging of any commercially available DCR system, permitting 16 complete channels in one CAMAC double-width module without exceeding CAMAC power limits. Built-in wideband direct-coupled discriminators feature reliable 120 MHz operation. Extremely stable input thresholds are internally variable from -80 mV to -500 mV for compatibility with a wide range of photomultipliers. Discrimi- nator output durations are internally preset to approximately 1.5 ns for optimum timing accuracy, independent of input amplitude and duration, eliminating the need for clipping cables and other adjustments.

The 2340A discriminator is a high-performance, modern discriminator -- not a compromise time-over-threshold device, or limiter. It differs from the best pre- sently available discriminators only in its more modest speed capability (120 MHz typical) and fixed output duration.

The logic channels, which seek a coincidence between each discriminator output and a common fast gate input, employ MECL III integrated circuits and provide coincidence resolving times under 2 ns. They represent the state-of-the-art in coincidence logic design and performance. The time coincidence between the common gate input and the 16 inputs are stored in a 16 bit fast buffer register for later readout under CAMAC commands. The facility for performing majority logic is provided by two front-panel summing outputs which are each driven by 8 logic channels. The output current of the summing circuit is proportional, in increments of 4 mA per register bit, to the number of coincidences stored in the register. Bridged high impedance outputs permit cascading any number of summing outputs. Other operating features include a front-panel clear input which responds to nega- tive logic levels and a built-in test mode.

The Model 2340A DCR is a member of LRS's CAMAC Series, a growing line of instruments which combine high performance with the flexibility and computer compatibility of the CAMAC standard.

SPECIFICATIONS

INPUT CHARACTERISTICS

Discriminator Inputs:

16, Lemo connectors; impedance 50ohm +/- 1%; direct- coupled; protected to +/- 10 volts for inputs <1 us; reflections <5% for 2 ns risetime; quiescent dc level <5 mV.

Input Threshold:

Internally adjustable from < -80 mV to > -500 mV; stability <0.2 mV/degC; no width dependence to 3 ns (approximately 130% at 2 ns).

Double Pulse Resolution:

10 ns max.; 8 ns typical

Gate Input:

One; Lemo connector; 50 ohm impedance; -600 mV or greater enables; minimum duration at full logic level (-750 mV), 2.0 ns; protected to +/- 100 V.

Clear Input:

One, Lemo connector: -600 mV or greater, 50 Q impedance; minimum duration, 10 ns; protected to +/- 100 V. 10 ns settling time after clear.

OUTPUT CHARACTERISTICS

Data Readout:

CAMAC function and address commands gate the 16 binary bits on to the 2 0 to 2 15 CAMAC dataway bus lines; logical 1,<=0.5 volts (0 to 16 mA); logical 0, open circuit (<=100 uA at 5.5 volts).

Summing Outputs:

2; one pair of high impedance bridged connectors for each set of 8 inputs; 4 mA +/-3% is presented for each register latched; maximum output into 25 ohm, -1 volt for a single or cascaded units (corresponds to 10 set registers); risetime, 2 ns (increasing to 4 for -1.0 volt); delay of leading edge of summing output from leading edge of discriminator input, 15 ns.

GENERAL

Coincidence Width:

Approximately equal to gate durations, independent of input amplitude or duration.

Time Slewing:

< 2ns.

Multiple Pulsing:

None, regardless of input amplitude or duration.

CAMAC Commands:

Z or C: Clears register, requires S2.
Q: A Q=1 response is generated in recognition of valid "read" (F0 or F2). An optional jumper allows both F25 and F9 to generate Q for a valid "N" and "AO".
I: Gate input is inhibited for duration of CAMAC inhibit command.

CAMAC Function Codes:

F0: Read group 1 register; requires "N" and "A0".
F2: Read and Clear group 1 register; requires "N", "40" and "S2".
F9: Clear Group 1 register; requires "N", "AO" and S2.
F25: Increment (test mode latches all channels); requires "N" and "S2".

Packaging:

CAMAC double-width module. Conforms to ESONE Report EUR 4100e standards.

Power Requirements:

Less than 16 watts, + 6 V, -24 V.

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SPECIFICATIONS
INPUT CHARACTERISTICS
Discriminator Inputs:	16, Lemo connectors; impedance 50ohm +/- 1%; direct- coupled; protected to +/- 10 volts for inputs <1 us; reflections <5% for 2 ns risetime; quiescent dc level <5 mV.
Input Threshold:	Internally adjustable from < -80 mV to > -500 mV; stability <0.2 mV/degC; no width dependence to 3 ns (approximately 130% at 2 ns).
Double Pulse Resolution:	10 ns max.; 8 ns typical
Gate Input:	One; Lemo connector; 50 ohm impedance; -600 mV or greater enables; minimum duration at full logic level (-750 mV), 2.0 ns; protected to +/- 100 V.
Clear Input:	One, Lemo connector: -600 mV or greater, 50 Q impedance; minimum duration, 10 ns; protected to +/- 100 V. 10 ns settling time after clear.
OUTPUT CHARACTERISTICS
Data Readout:	CAMAC function and address commands gate the 16 binary bits on to the 2 0 to 2 15 CAMAC dataway bus lines; logical 1,<=0.5 volts (0 to 16 mA); logical 0, open circuit (<=100 uA at 5.5 volts).
Summing Outputs:	2; one pair of high impedance bridged connectors for each set of 8 inputs; 4 mA +/-3% is presented for each register latched; maximum output into 25 ohm, -1 volt for a single or cascaded units (corresponds to 10 set registers); risetime, 2 ns (increasing to 4 for -1.0 volt); delay of leading edge of summing output from leading edge of discriminator input, 15 ns.
GENERAL
Coincidence Width:	Approximately equal to gate durations, independent of input amplitude or duration.
Time Slewing:	< 2ns.
Multiple Pulsing:	None, regardless of input amplitude or duration.
CAMAC Commands:	Z or C: Clears register, requires S2. Q: A Q=1 response is generated in recognition of valid "read" (F0 or F2). An optional jumper allows both F25 and F9 to generate Q for a valid "N" and "AO". I: Gate input is inhibited for duration of CAMAC inhibit command.
CAMAC Function Codes:	F0: Read group 1 register; requires "N" and "A0". F2: Read and Clear group 1 register; requires "N", "40" and "S2". F9: Clear Group 1 register; requires "N", "AO" and S2. F25: Increment (test mode latches all channels); requires "N" and "S2".
Packaging:	CAMAC double-width module. Conforms to ESONE Report EUR 4100e standards.
Power Requirements:	Less than 16 watts, + 6 V, -24 V.