The LRS Model 2341 Coincidence Register ("pattern unit") offers fast storage functions in computer-compatible CAMAC standard packaging. The integrated circuit design affords the highest density packaging, permitting 16 complete channels in one CAMAC double-width module without exceeding CAMAC power limits.
The 2341 operates from standard NIM logic levels. The logic channels, which seek a coincidence between each input and a common fast gate input, employ MECL Ill integrated circuits and provide coincidence resolving times under 2 ns. They represent the state-of-the-art in coincidence logic design and performance. The time coincidence between the common gate input and the 16 inputs are stored in a 16 bit fast buffer register for later readout under CAMAC commands. The facility for performing majority logic is provided by two front-panel summing outputs which are each driven by 8 logic channels. The output current of the summing circuit is proportional, in increments of 4 mA per register bit, to the number of coincidences stored in the register. Bridged high impedance outputs permit cascading any number of summing outputs. Other operating features include a front-panel clear input which responds to negative logic levels and a built-in test mode.
The Model 2341 Coincidence Register is a member of LRS's CAMAC Series, a growing line of instruments which combine high performance with the flexibility and computer compatibility of the CAMAC standard. SPECIFICATIONS
INPUT CHARACTERISTICS Discriminator Inputs: 16, Lemo connectors; impedance 50 Ohm +/- 5%; direct-coupled; protected to +/- 10 volts for inputs < 1 us; reflections < 10% for 2 ns risetime. Input Threshold: Accepts standard AEC - NIM fast logic levels (-500 mV nominal). Double Pulse Resolution: 10 ns max.; 8 ns typical . Gate Input: One; Lemo connector; 50 Ohm impedance; -600 mV or greater enables; minimum duration at full logic level (-750 mV), 2.0 ns; protected to +/- 100 V. Internal delay of 5 ns. Clear Input: One, Lemo connector; -600 mV or greater, 50 Ohm impedance; minimum duration, 10 ns; protected to +/- 100 V. 10 ns settling time after clear. OUTPUT CHARACTERISTICS Data Readout: CAMAC function and address commands gate the 16 binary bits on to the 20 to 215 CAMAC dataway bus lines; logical 1, < 0.5 volts (0 to 16 mA); logical 0, open circuit (<= 100 uA at 5.5 volts). Summing Outputs: 2; one pair of high impedance bridged connectors for each set of 8 inputs; 4 mA +/- 3% is presented for each register latched; maximum output into 25 Ohm, -1 volt for a single or cascaded units (corresponds to 10 set registers); risetime, 2 ns (increasing to 4 for -1 .0 volt); delay of leading edge of summing output from leading edge of discriminator input, 15 ns.