LeCroy 2341A 16 Channel Coincidence Register

CAMAC Model 2341A 16-Channel Coincidence Register

* 16 channels in single-width module ... less space than that required by other designs.
* Summing outputs provide fast trigger capability ... organized in two groups of eight registers for use in multiplicity decisions.
* Fast clear input ... permits use of loose pretrigger (so summing output can participate in final logic decision) without deadtime generating dataway clearing operation.
* Narrow coincidence widths ... High speed design permit coincidence width as narrow as 1 nsec.
* Input double-pulse resolution <10 nsec ... assures high efficiency even in high count rate applications.
* Accepts input amplitudes as low as -100 mV ... permits triggering even after substantial attenuation from long cable delays.

The LeCroy Model 2341A Coincidence Register ("pattern unit") offers fast storage functions in computer-compatible CAMAC standard packaging. The integrated circuit design affords high density packaging, permitting 16 complete channels in one CAMAC single-width module.

The 2341A operates from standard NIM logic levels. The logic channels, which seek a coinci- dence between each input and a common fast gate input, employ MECL Ill integrated circuits and provide coincidence resolving times under 2 nsec. Logical "l" data levels, representing the time coincidence between the common gate and the 16 inputs, are stored in a 16-bit fast buffer register for later readout under CAMAC commands. The facility of performing majority logic is provided by two rear-panel summing outputs which are each driven by 8 logic chan- nels. The output current of the summing circuit is proportional, in increments of 4 mA per regis- ter bit, to the number of coincidences stored in the register. Bridged high impedance outputs permit cascading any number of summing outputs. Other operating features include a front- panel clear input which responds to negative logic levels and a built-in test mode.

The Model 2341A Coincidence Register is a member of LeCroy's CAMAC Series, a growing line of instruments which combine high performance with the flexibility and computer com- patibility of the CAMAC standard.

SPECIFICATIONS CAMAC Model 2341A 16-CHANNEL COINCIDENCE REGISTER

INPUT CHARACTERISTICS

Inputs:

16, Lemo connectors; impedance 50 Ohm +/-5%; direct-coupled; protected to +/-10 volts for inputs <1 usec; reflections <10% for 2 nsec risetime.

Required Input Level:

Adjustable from -100 mV to -1.0 V with rear-panel potentiometer.

Double Pulse Resolution:

10 nsec max.; 8 nsec typical.

Gate Input:

One; Lemo connector; 50 Ohm impedance; -600 mV or greater enables; mini- mum duration at full logic level (-750 mV), 2.0 nsec; protected to +/-100 V. Should precede inputs by at least 3 nsec.

Clear Input:

One, Lemo connector: -600 mV or greater, 50 Ohm impedance; minimum du- ration, 10 nsec; protected to +/-100 V. 10 nsec settling time after clear.

OUTPUT CHARACTERISTICS

Data Readout:

CAMAC function and address commands gate the 16 binary bits on to the 20 to 1215 CAMAC dataway bus lines; logical 1, <=0.5 volts (O to 16 mA); logical 0, open circuit (- 100 uA at 5.5 volts).

Summing Outputs:

2; one pair of high impedance bridged connectors for each set of 8 inputs; 4 mA +/- 3% is presented for each register latched; maximum output into 25 Ohm, -1 volt for single or cascaded units (corresponds to 10 set registers); risetime, 4 nsec (increasing slightly for multiple levels); delay of leading edge of summing output from leading edge of input, 20 nsec.

GENERAL

Coincidence Width:

1 nsec up, determined by input and gate pulse durations.

CAMAC Commands:

Z or C:

Clears register, requires S2.

1:

Gate Input is inhibited for duration of CAMAC inhibit commands.

Q:

A Q=l response is generated in recognition of an F(O), F(2), F(9), or F(25) for a valid N and A(O), but there will be no response (Q=O) under any other condition.

X:

An X=l (Command Accepted) response is generated when a valid F, N, and A command is generated.

CAMAC Function Codes:

F(O):

Read group 1 register; requires N and A(O).

F(2):

Read and Clear group 1 register; requires N, A(O), and S2.

F(9):

Clear Group 1 register; requires N, A(O), and S2.

F(25):

Increment (test mode latches all channels); requires N and S2.

Packaging:

CAMAC single-width module. Conforms to ESONE Report EUR 4100 or IEEE #583 standards.

Power Requirements:

+6 V at 500 mA
-6 V at 800 mA
-24 V at 65 mA

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INPUT CHARACTERISTICS
Inputs:	16, Lemo connectors; impedance 50 Ohm +/-5%; direct-coupled; protected to +/-10 volts for inputs <1 usec; reflections <10% for 2 nsec risetime.
Required Input Level:	Adjustable from -100 mV to -1.0 V with rear-panel potentiometer.
Double Pulse Resolution:	10 nsec max.; 8 nsec typical.
Gate Input:	One; Lemo connector; 50 Ohm impedance; -600 mV or greater enables; mini- mum duration at full logic level (-750 mV), 2.0 nsec; protected to +/-100 V. Should precede inputs by at least 3 nsec.
Clear Input:	One, Lemo connector: -600 mV or greater, 50 Ohm impedance; minimum du- ration, 10 nsec; protected to +/-100 V. 10 nsec settling time after clear.
OUTPUT CHARACTERISTICS
Data Readout:	CAMAC function and address commands gate the 16 binary bits on to the 20 to 1215 CAMAC dataway bus lines; logical 1, <=0.5 volts (O to 16 mA); logical 0, open circuit (- 100 uA at 5.5 volts).
Summing Outputs:	2; one pair of high impedance bridged connectors for each set of 8 inputs; 4 mA +/- 3% is presented for each register latched; maximum output into 25 Ohm, -1 volt for single or cascaded units (corresponds to 10 set registers); risetime, 4 nsec (increasing slightly for multiple levels); delay of leading edge of summing output from leading edge of input, 20 nsec.
GENERAL
Coincidence Width:	1 nsec up, determined by input and gate pulse durations.
CAMAC Commands:
Z or C:	Clears register, requires S2.
1:	Gate Input is inhibited for duration of CAMAC inhibit commands.
Q:	A Q=l response is generated in recognition of an F(O), F(2), F(9), or F(25) for a valid N and A(O), but there will be no response (Q=O) under any other condition.
X:	An X=l (Command Accepted) response is generated when a valid F, N, and A command is generated.
CAMAC Function Codes:
F(O):	Read group 1 register; requires N and A(O).
F(2):	Read and Clear group 1 register; requires N, A(O), and S2.
F(9):	Clear Group 1 register; requires N, A(O), and S2.
F(25):	Increment (test mode latches all channels); requires N and S2.
Packaging:	CAMAC single-width module. Conforms to ESONE Report EUR 4100 or IEEE #583 standards.
Power Requirements:	+6 V at 500 mA -6 V at 800 mA -24 V at 65 mA