* 16 channels in single-width module ... half the space required
by other designs. * Input double pulse resolution < 10 ns ...
assures high efficiency even in high count rate applications.
* Fast clear input ... permits use of loose pretrigger (so summing
output can participate in final logic decision) without deadtime
generating dataway clearing operation.
* Summing outputs provide output DC level proportional to number of
latched registers ... organized in two groups of eight registers for
use in multiplicity decisions.
* Narrow coincidence widths ... High speed coincidence circuit
permits coincidence width as narrow as 1 ns.
* Built-in test mode ... Increment Function Code latches all channels
regardless of state of gate input.
* Power dissipation less than CAMAC maximum ... assures long,
reliable operation and does not require special power supplies.
The LRS Model 2341S Coincidence Register ("pattern unit") offers fast storage functions in computer-compatible CAMAC standard packaging. The integrated circuit design affords high density packaging, permitting 16 complete channels in one CAMAC single-width module without exceeding CAMAC power limits.
The 2341S operates from standard NIM logic levels. The logic channels, which seek a coincidence between each input and a common fast gate input,employ MECL III integrated circuits and provide coincidence resolving times under 2 ns. They represent the state-of- the-art in coincidence logic design and performance. Logical "l " data levels, representing the time coincidence between the common gate and the 16 inputs, are stored in a 16-bit fast buffer register for later readout under CAMAC commands. The facility of performing majority logic is provided by two rear-panel summing outputs which are each driven by 8 logic channels. The output current of the summing circuit is proportional, in increments of 4 mA per register bit, to the number-of coincidences stored in the register. Bridged high impedance outputs permit cascading any number of summing outputs. Other operating features include a front-panel clear input which responds to negative logic levels and a built-in test mode.
The Model 2341 S Coincidence Register is a member of LRS's CAMAC Series, a growing line of instruments which combine high performance with the flexibility and computer compatibility of the CAMAC standard.
SPECIFICATIONS CAMAC Model 2341 S 16-CHANNEL COINCIDENCE REGISTER
|
INPUT CHARACTERISTICS |
|
|
Inputs: |
16, Lemo connectors; i impedance 50 Ohm +/- 5%; direct-coupled; protected to +/- 1 0 volts for inputs < 1 Ms; reflections < 10% for 2 ns risetime. |
|
Input Threshold: |
Accepts standard AEC/NIM fast logic levels (-500 mV nominal). |
|
Double Pulse Resolution: |
10 ns max.; 8 ns typical. |
|
Gate Input: |
One; Lemo connector; 50 Ohm impedance; -600 mV or greater enables; minimum duration at full logic level (-750 mV), 2.0 ns; protected to +/- 100 V. Should precede inputs by at least 4 ns. |
|
Clear Input: |
One, Lemo connector: -600 mV or greater, 50 Ohm impedance; minimum dura- tion, 1 0 ns; protected to +/- 1 00 V. 1 0 ns settling time after clear. |
|
OUTPUT CHARACTERISTICS |
|
|
Data Readout: |
CAMAC function and address commands gate the 16 binary bits on to the 20 to 215 CAMAC dataway bus lines; logical 1, -- 0.5 volts (0 to 16 mA); logical 0, open circuit (<= 100 uA at 5.5 volts). |
|
Summing Outputs: |
2; one pair of high impedance bridged connectors for each set of 8 inputs; 4 mA +/- 3% is presented for each register latched; maximum output into 25 Ohm, -1 volt for single or cascaded units (corresponds to 10 set registers); risetime, 4 ns (increasing slightly for multiple levels); delay of leading edge of summing output from leading edge of input, 20 ns. |
|
GENERAL |
|
|
Coincidence Width: |
1 ns up, determined by input and gate pulse durations. |
|
CAMAC Commands: |
|
|
Z or C: |
Clears register, requires S2. |
|
1: |
Gate Input is inhibited for duration of CAMAC inhibit commands. |
|
Q: |
A Q = 1 response is generated in recognition of an F(O), F(9), or F(25) for a valid N and A(O), but there will be no response (Q=O) under any other condition. |
|
X: |
An X=l (Command Accepted) response is generated when a valid F, N, and A command is generated. |
|
CAMAC Function Codes: |
|
|
F(O): |
Read group 1 register; requires N and A(O). |
|
F(2): |
Read and Clear group 1 register; requires N, A(O), and S2. |
|
F(9): |
Clear Group 1 register; requires N, A(O), and S2. |
|
F(25): |
Increment (test mode latches all channels); requires N and S2. |
|
Packaging: |
CAMAC single-width module. Conforms to ESONE Report EUR 4100e standards. |
|
Power Requirements: |
+6 V at 320 mA |