CAMAC ECLine Model 2365 Octal Logic Matrix; 16 x 8

The Model 2365 Octal Logic Matrix is a versatile programmable100 MHz logic unit designed for trigger appli- cations involving high speed logic arrays. It allows complete programmability of all of the logic functions which it provides. The unit is ideal for specifying triggers based upon roadways through hodoscope arrays. An analog multiplicity output via a front panel Lemo Connector is provided for triggering on multi track events.

The Model 2365 accepts 16 differential ECL inputs. These signals are applied to each of the eight indepen- dent logic channels. The outputs are differential ECL levels on a standard ECLine header. Two outputs are provided per channel. The 16-bit input size is most useful for large counter arrays. Wide 16-bit input width minimizes the need for cascading of logic units. This results in lower cost and shorter overall trigger propaga- tion delay.

The logic matrix for the Model 2365 is shown in figure 1. Each channel is comprised of a series of program- mable select gates which allow a wide variety of boolean logic combinations to be assigned. These functions include:

 Input selection - switchyard
 Complementing - input and output
 OR - logic fan-in
 AND - coincidence
 Veto - via complementing function

A CAMAC-loadable Test Register, CTR, in the Model 2365 adds to the versatility of the unit. This register may be used as one of the diagnostics for complete CAMAC checkout of the trigger logic. The 16-bit pattern, loaded into the Test Register, may be applied to the inputs of the logic matrix by a CAMAC command, thereby deselecting 16 front panel logic inputs. This operation simulates logic inputs for testing purposes. The eight outputs of the logic matrix may also be read via CAMAC.

The CTR also allows for a sophisticated veto. A consequence of the versatility of the Logic Matrix is that the quiescent states of its outputs are defined by the application. For this reason, the Test Register is used in the veto circuit. Application of a fast front panel ECL Veto Enable signal sets the inputs to the pattern stored in the Test Register for the duration of the Veto Enable pulse (>= 10 nsec). If the quiescent input levels are loaded in the Test Register, proper veto operation is achieved.

The Model 2365 provides many logic functions never before feasible in such a compact format. Together with the other members of the ECLine logic family, it allows an economical and versatile prompt trigger to be con- figured under computer control.

SPECIFICATIONS CAMAC ECLine Model 2365 Octal Logic Matrix; 16 x 8

INPUT CHARACTERISTICS
Number of Inputs:	16, direct coupled; 100 Ohm, high Z by user option; reflections < 10% for signals of >= 2 nsec risetime.
Input Width:	>= 5 nsec fwhm
Maximum Rate:	>= 100 MHz
Input Connector:	17-pair front-panel header
Veto Enable:	Differential ECL input via two pin header. Input impedance 100 Ohm, high Z by simple user modification. When asserted, the contents of the 16-bit CAMAC- programmable test register (CTR) are applied to the logic matrix overriding the front panel inputs. Minimum width 5 nsec. Must precede the Input by >= 5 nsec.
OUTPUT CHARACTERISTICS
Logic Outputs:	Two per channel, sixteen total; ECL levels via a 34-pin header with pinouts to match the ECLine standard. Output width equals duration of logic condition.
Output Rate:	>= 100 MHz
Propagation Delay:	< 10 nsec
Analog Multiplicity:	Front panel Lemo output provides 1 mA for each logic matrix output in the logical 1 state. Rise and falltime < 4 nsec.
MEMORY PROTECTION
Continuous Memory:	Memory battery back up. This feature preserves contents of memory and CTR during CAMAC power down. Life of the battery is two years of operation.
MODE CONTROL
Front Panel:	The sixteen ECL input levels are applied to the octal logic matrix (8LM). Selected by the CAMAC Mode Selector bit.
Test:	The contents of the 16-bit CTR are applied to the 8LM. Selected by the Mode Selector bit.
Veto:	The contents of the CTR are applied to the 8LM. Selected via front panel Veto Enable input.
SOFTWARE SELECTED LOGIC COEFFICIENTS
Ai,j	AND Selector. When set to logical 1, routes the compliment of the ith input to the j th logic matrix OR. When Aij = 0, compliment unused.
Bi,j	OR Selector. When set to logical 1, routes the ith input to the jth logic Matrix OR. When Bij = 0 normal signal unused.
Cj	Output Complimentor. When set to logical 1, <= routes the compliment of the jth logic matrix OR to the ith output. When Cj = 0, the normal OR is used.
CAMAC COMMANDS
F(O)-A(O):	Read 18 sixteen-bit programming words. Eighteen successive read commands must be done to complete read operation and reinitialize the 2365 for logical operation.
F(O)-A(l):	Read 16-bit input pattern. The ECL logic levels at the input must be static dur- ing the read cycle.
F(O)-A(2):	Read 8-bit output word. Outputs must be static during the read cycle.
F(O)-A(3):	Read Mode Selector bit (O indicates Front Panel mode, 1 indicates Test mode).
F(9)-A(O):	Initialize the 2365. This operation is required on power up.
F(16)-A(O):	Write eighteen 16-bit programming words. Requires 18 successive write commands.
F(l6)-A(3):	Write Mode Selector bit (O indicates Front Panel mode, 1 indicates Test mode).
X:	An X= 1 response is generated for any valid N-F-A.
Q:	A Q = 1 response is generated for F(O)-A(O) and F(l 6)-A(O). A Q = 0 response is generated at the 18th successive command (terminal count). This Q response is valid only if a F(9)-A(O) has been performed at power up.
GENERAL
Packaging:	In confomance with CAMAC standard for nuclear modules (ESONE Commit- tee Report EUR4100 or IEEE Report 583. RF-shielded CAMAC #1 module.
Current Requirements:	< 400 mA at + 6V < 2.5 A at - 6V