CAMAC Model 2371 ECLine Data Register

* General Purpose Data Register
* 16 Data Inputs with Strobe and Enable
* Buffered Outputs
* ECLine Compatible
* Ideal for Trigger Processors
* Ideal for Hodoscopes

The Model 2371 is a single-width CAMAC module used to latch 16-bit data patterns and present them at two identical ECLine standard front-panel ports. It also allows the pattern to be read via CAMAC. The 16-bit input pattern is latched at the leading edge of the AND of the front-panel ENABLE and Strobe signals.

The module also provides two ECL Output Ready strobes to indicate that the contents of the latch have been updated. This strobe is delayed by 60 nsec from the start of the Input Enable Strobe condition. A board-mounted potentiometer allows the strobe to be adjusted over the range 30-90 nsec. This feature allows 16-bit datawords to be cap- tured and delayed to match the timing of other system elements.

The Model 2371 may be used for hodoscope and wire chamber applications, espe- cially if the latched signals must be incorporated in second level trigger logic. Complex trigger decision and pattern generation can be performed with the Model 2371 and LeCroy ECLine programmable trigger modules.

The Model 2371 also may be used as a register in ECLine data handler trigger applica- tions. It is fully compatible with the ECLport on the 4300 Series FERA ADC System and the 2700-Series PCOS Ill System. See LeCroy Publication P2 and Application Note 24A for more details. SPECIFICATIONS Model 2371 ECLine Data Register

INPUTS

Data In:  16 bits, ECL levels via a 17-pair header. Pin-outs match the
   ECLine standard. Input impedance 100 Ohm +/-5% high impedance
   by a simple user modification. Minimum pulse width 10 nsec.

Input Enable:  Differential ECL input via front-panel 2-pin header. Impedance
   100 Ohm +/-5%. Enables the Strobe signal. Minimum width
   10 nsec. Unused input remains in the logical 1 state.

Input Strobe:  Differential ECL input via front-panel 2-pin header. Impedance
   100 Ohm +/-5%. The leading edge of the Input Strobe latches the
   state of the 16-bit Data input. Minimum width 10 nsec.

OUTPUTS

Data Out:  Two identical 16-bit outputs on front panel. ECL levels pre-
   sented via two identical 17-pair headers with pin-outs to match
   the ECLine standard. Outputs are updated on receipt of an In-
   put Strobe.

Output Ready:  Two identical differential ECL outputs, each via a 2-pin connec-
   tor on front panel. Output becomes valid 60 nsec +/-10% after
   the leading edge of the Input Strobe and remains valid until the
   leading edge of the next Input Strobe. Other delay times may
   be set via the Delay Adjustment potentiometer. See below.

CAMAC COMMANDS

N-F(O)-A(O)  Read 16-bit word.

N-F(9), any A  Clear Module.

Z,C  Clear Module.

X:  An X=l response is generated for any valid CAMAC command.

GENERAL

Delay Adjust:  Board-mounted potentiometer. Used to set the delay between
   the Input Enable leading edge and the Output Ready leading
   edge. Factory set to 60 nsec +/-10%. Adjustable over the
   range 30-90 nsec.

Propagation Delay: Less than 15 nsec from the Input Strobe (leading edge) until the
   front-panel output data is valid.

Current Requirements: +6 V, 300 mA
   -6 V, 1.7 A

Packaging:  In conformance with CAMAC standard for nuclear modules
   (ESONE Committee Report EUR4100 or IEEE Report 583). RF-
   shielded CAMAC #1 module.