LeCroy 2375 Data Stack Module

* Trigger Processing
* Multiple Event Buffer
* High Speed: 50 nsec cycle time
* High Density: 256 sixteen-bit words
* Dual Ported: simultaneous read/write
* Self Sequencing

The Model 2375 is a Data Stack designed for use with the LeCroy family of ECLine Trigger Processor modules. It is a fast 256 x 16 memory with separate read and write ECLports, based upon the Fermilab ECL 4 module. A block diagram of the Stack is shown below. The Model 2375 is ideal for rapid processing of lists of data from a variety of sources, such as the ECLport outputs of the PCOS III and FERA system. It may also be used as an Event Buffer in conjunction with these data acquisition systems.

The Write ECLport of the Model 2375 is initialized by a Master Reset (MRST) pulse which resets the internal Read and Write Pointers (RP and WP). The Write ECLport accepts 16-bit datawords at up to a 20 MHz rate. Datawords are latched into the port by an ECL Write Enable (WE) edge and loaded into sequential locations beginning with zero. Fifty nsec later a Write Output Ready (WR) level is asserted. If the write operation is performed during a read operation, the write is delayed by up to 35 nsec. Both operations are correctly performed, however. The upper 3 bits of the dataword may be used by the write Steering Logic to accept or reject the write strobe. A side-panel switch allows each of the eight possibilities to be separately enabled. This allows the stack to be loaded with one type of data (e.g. x) while ignoring another type (e.g. y).

The Model 2375 offers sequential readout. Read operations are initiated by read enable RE. Within 35 nsec, the appropriate dataword is returned along with a Read Ready signal called RR. The Read ECLport may be used without regard to the operation of the Write ECLport. If the read operation is performed during a write operation, the read is delayed by up to 50 nsec. Both operations are correctly performed, however.

Read operations may commence before the write operations have been completed. The All Data In (ADI) signal at the Write ECLport is used to signal that the Write operation is complete.

Application of RE pulse returns the dataword and an RR edge and advances the internal Read Pointer. If the Write Pointer is less than the Read Pointer, the Data Stack suspends the dataword response, pending either another write operation or an ADI (all data in) edge. If another dataword is loaded into the Model 2375, it is output in response to the read command alone with an RR edge. If an ADI level is received, Read Overflow (ROF) edge is output. The ROF also resets the Read Pointer so that a subsequent read operation causes the stack to "wrap around" and return the dataword in the bottom of the memory. Stack modules can be wired to act as a series of Nested Do Loops. See Application Note AN-24A.

The Model 2375 is packaged in a single-width CAMAC module. It employs the popular ECLine stan- dard for signals. It provides versatility and sophistication to trigger logic.

SPECIFICATIONS

GLOSSARY OF TERMS

ADI: All Data In -- Input
MRST: Master Reset -- Input
ROF: Read Overflow -- Output
RP: Read Pointer -- Internal
RE: Read Enable -- Input
RR: Read Ready -- Output
RRST: Read Reset -- Input
WOF: Stack Full (write overflow) -- Output
WE: Write Enable -- Input
WP: Write Pointer -- Internal
WR: Write Ready -- Output

WRITE ECLport

Write Reset (MRST):

A front-panel differential ECL input via a two-pin connector. Used to set the Write Address Pointer and Read Address Pointer to zero. Minimum width 10 nsec. Reset time 30 nsec.

Write Enable (WE):

A front-panel differential ECL input via two bridged 2-pin connectors. Used to actuate a write operation. The action of the WE leading edge is to write the Dataword presented at the W ECLport and advance the Write Address Pointer by 1. Write operation requires 50 nsec.

W Dataword (DATA I):

A front-panel differential ECL input for a 16-bit dataword. Supplied via an ECLine stan- dard 17-pair header. The Data I must be settled before application of the WE strobe. Minimum duration: 10 nsec.

All Data In (ADI):

A front-panel differential ECL input via two bridged 2-pin connectors. When unused, it is set to the logical 1 condition. An AD I = 0 suspends responses to a Read request if the read address exceeds the Write Address Pointer. A response occurs either when ADI = 1 or after another write operation is performed. If ADI = 1 and the read address exceeds the Write Address Pointer, an ROF pulse is returned and the Read Address pointer is set to zero. Cleared by MRST.

Write Ready (WR):

A front-panel differential ECL output via two bridged 2-pin connectors to indicate the completion of a write operation.

Write Overflow (WOF):

A front-panel differential ECL output level via a 2-pin connector indicates that 256 writes have been performed.

READ ECLport

Read Reset (RRST):

A front-panel differential ECL input via a 2-pin connector used to set the Read Address Pointer to zero. Minimum width: 10 nsec. Reset time 30 nsec.

Read Enable (RE):

A front-panel differential ECL input via two bridged 2-pin connectors. Used to initiate a Stack Read operation and to advance the Read Address Pointer by 1. The leading edge of the RE provides the dataword addressed by the Read Address Pointer at the Read ECLport's Data 0 Connector. An RR edge is provided 5 nsec after the Data 0 word is settled. Read operation requires 35 nsec.

R Dataword (Data 0):

A front-panel differential ECL output of a 16-bit dataword. Supplied via an ECLine standard 17-pair header.

Read Overflow (ROF):

A front-panel differential ECL output via 2-pin connector. Indicates that the read ad- dress exceeds the maximum address written into since the last MRST operation.

Read Ready (RR):

A front-panel differential ECL output via two bridged 2-pin connectors. Indicates that the read operation is complete and that data is valid at the Data 0 connector.

CAMAC COMMANDS

F(0) - A(0):

Read 16-bit dataword from memory as addressed by Read Pointer (RP). Increment RP.

F(0) - A(1):

Read 8-bit RP

F(0) - A(4):

Read 8-bit Write Pointer (WP)

F(9) - A(0):

Master Reset (MRST)

F(16) - A(0):

Write 16-bit dataword to memory location addressed by WP. Increment WP.

F(16) - A(1):

Write 8-bit RP

F(16) - A(4):

Write 8-bit WP

Q:

A Q =1 response is generated for F(0)-A(0) and F(16)- A(0). A Q = 0 response is generated for F(0)-A(0) when the RP>=WP and RP>0. A Q = 0 response is generated for F(16)- A(0) when WP = 255.

X:

An X = 1 response is generated for any valid N F A.

GENERAL

Packaging:

In conformance with CAMAC standard for nuclear modules (ESONE Committee Report EUR4100 or IEEE Report 583.) RF-shielded CAMAC #1 module.

Power Requirements:

+/-6 V, <25 W

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SPECIFICATIONS
GLOSSARY OF TERMS	ADI: All Data In -- Input MRST: Master Reset -- Input ROF: Read Overflow -- Output RP: Read Pointer -- Internal RE: Read Enable -- Input RR: Read Ready -- Output RRST: Read Reset -- Input WOF: Stack Full (write overflow) -- Output WE: Write Enable -- Input WP: Write Pointer -- Internal WR: Write Ready -- Output
WRITE ECLport
Write Reset (MRST):	A front-panel differential ECL input via a two-pin connector. Used to set the Write Address Pointer and Read Address Pointer to zero. Minimum width 10 nsec. Reset time 30 nsec.
Write Enable (WE):	A front-panel differential ECL input via two bridged 2-pin connectors. Used to actuate a write operation. The action of the WE leading edge is to write the Dataword presented at the W ECLport and advance the Write Address Pointer by 1. Write operation requires 50 nsec.
W Dataword (DATA I):	A front-panel differential ECL input for a 16-bit dataword. Supplied via an ECLine stan- dard 17-pair header. The Data I must be settled before application of the WE strobe. Minimum duration: 10 nsec.
All Data In (ADI):	A front-panel differential ECL input via two bridged 2-pin connectors. When unused, it is set to the logical 1 condition. An AD I = 0 suspends responses to a Read request if the read address exceeds the Write Address Pointer. A response occurs either when ADI = 1 or after another write operation is performed. If ADI = 1 and the read address exceeds the Write Address Pointer, an ROF pulse is returned and the Read Address pointer is set to zero. Cleared by MRST.
Write Ready (WR):	A front-panel differential ECL output via two bridged 2-pin connectors to indicate the completion of a write operation.
Write Overflow (WOF):	A front-panel differential ECL output level via a 2-pin connector indicates that 256 writes have been performed.
READ ECLport
Read Reset (RRST):	A front-panel differential ECL input via a 2-pin connector used to set the Read Address Pointer to zero. Minimum width: 10 nsec. Reset time 30 nsec.
Read Enable (RE):	A front-panel differential ECL input via two bridged 2-pin connectors. Used to initiate a Stack Read operation and to advance the Read Address Pointer by 1. The leading edge of the RE provides the dataword addressed by the Read Address Pointer at the Read ECLport's Data 0 Connector. An RR edge is provided 5 nsec after the Data 0 word is settled. Read operation requires 35 nsec.
R Dataword (Data 0):	A front-panel differential ECL output of a 16-bit dataword. Supplied via an ECLine standard 17-pair header.
Read Overflow (ROF):	A front-panel differential ECL output via 2-pin connector. Indicates that the read ad- dress exceeds the maximum address written into since the last MRST operation.
Read Ready (RR):	A front-panel differential ECL output via two bridged 2-pin connectors. Indicates that the read operation is complete and that data is valid at the Data 0 connector.
CAMAC COMMANDS
F(0) - A(0):	Read 16-bit dataword from memory as addressed by Read Pointer (RP). Increment RP.
F(0) - A(1):	Read 8-bit RP
F(0) - A(4):	Read 8-bit Write Pointer (WP)
F(9) - A(0):	Master Reset (MRST)
F(16) - A(0):	Write 16-bit dataword to memory location addressed by WP. Increment WP.
F(16) - A(1):	Write 8-bit RP
F(16) - A(4):	Write 8-bit WP
Q:	A Q =1 response is generated for F(0)-A(0) and F(16)- A(0). A Q = 0 response is generated for F(0)-A(0) when the RP>=WP and RP>0. A Q = 0 response is generated for F(16)- A(0) when WP = 255.
X:	An X = 1 response is generated for any valid N F A.
GENERAL
Packaging:	In conformance with CAMAC standard for nuclear modules (ESONE Committee Report EUR4100 or IEEE Report 583.) RF-shielded CAMAC #1 module.
Power Requirements:	+/-6 V, <25 W