LeCroy 2731A 32 Channel Delay and Latch

PCOS III Dedicated CAMAC Model 2731A 32 Channel Delay and Latch

The LeCroy Model 2731A has been designed as a central element for MWPC encoding. Each 2731A module accepts 32 dif- ferential ECL inputs on two ECLine standard 17-pair front-panel headers. Using LeCroy's unique Ripplethru delay, each signal input is delayed by a programmable interval from 300 to 750 nsec. The delayed data are presented to edge-triggered latches which can be activated by coincidence gates as short as 25 nsec.

Computer control of the threshold of chamber discriminators is provided in the Model 2731A via an 8-bit digital-to-analog converter. This threshold programming voltage is provided at both signal input headers. The LeCroy 2735-Series chamber cards use this voltage for setting the chamber threshold.

The Model 2731A allows inclusion of the wire chamber data in the first and second level triggers. On-board prompt and latched signals may be wired OR'd in an arbitrary way. Additionally, two front-panel PASS OR pins may be used to allow the Prompt and Latched OR's to cross module boundaries. In this way, up to 16 signals are generated, which are availble at the front panel as differential ECL outputs for trigger purposes. These provisions allow the Model 2731A to be custom-tailored to the experimental trigger.

LeCroy's Ripplethru circuit provides delay with little dead time. It offers 300 nsec to 750 nsec of delay with a double pulse resolution of typically 100 nsec. This unique delay scheme offers excellent stability and interchannel matching (< +/- 10 nsec) while providing CAMAC programmability or "electronic cable cutting', The Coincidence Gate, Test Input Signal, and Fast Clear inputs are applied to the 2731A module via the CAMAC Dataway, eliminating the need for costly fanout. The signals are applied to the Model 2738 PCOS Ill Controller which controls the Dataway. The Coincidence Gate defines the time inter- val for which the "wire" latches are active. Wire discriminator signals which are received and passed through the Ripplethru delay are latched within the Model 2731A by a Coincidence Gate.

Comprehensive test circuits have been built into the PCOS Ill System. In addition to test inputs on the chamber card, the 2731A can be separately tested. It has provisions for application of logic pulses to the 32 inputs. A 32-bit mask allows each of the test inputs to be separately enabled and disabled. In this way, the 2731A circuitry and the external track recognition circuitry can both be tested. Also, a front-panel auxiliary test connector facilitates testing of threshold voltage, internal delay and total delay (2731A delay plus external cabling delay).

The Model 2731A is to be used in a dedicated CAMAC crate using the Model 2738 in the controller station. In this configura- tion, the 2731A modules can be read out at 10 x CAMAC speed, 100 nsec per 32-bit word. Data may then be cluster-compacted by the Model 2738. The concentrated cluster data may then be transferred to a LeCroy standard DATABUS for readout via a Model 4299 DATABUS Interface. Up to 16 system controllers may be connected to a single 4299. In addition, other LeCroy DATABUS systems may be read out along with the 2738 crates.

The Model 2731A is an advanced version of the PCOS Ill Delay and Latch module and is fully downward compatible with previous PCOS Ill hardware and software modules.

Specifications

INPUTS

IN A, IN B:

32 differential ECL inputs via two 17-pair front-panel headers. Input impedance 112 +/-2ohm. input configuration com- patible with LeCroy ECLine logic standard. Minimum pulse width 10 nsec.

Coincidence Gate:

Two differential ECL inputs applied from the Model 2738 via the CAMAC connector. Board-mounted jumper selects input El or input E2. Minimum width 30 nsec.

Test Input:

Two differential ECL inputs applied from the Model 2738 via the CAMAC connector Board mounted jumper selects input E3 or input E4. Minimum width 6O nsec. Applies a test input via the 32 pattern gates to the Ripplethru inputs. Test level must be logical "zerd" for data acquisition. Model 2731A should be inhibited during Test.

Clear:

Applied by the 2738 via CAMAC Dataway. Transmitted as an ECL pulse. Clears all latches within 30 nsec. Minimum width 100 nsec.

Inhibit:

Applied by the 2738 via the CAMAC Dataway. Common inhibit line set via programmable bit in the 2738 disables all 32 ECL inputs. Should be set when applying Test pulse.

RIPPLETHRU DELAY CIRCUIT

Delay Variations:

+/- 5 nsec typical, +/- 10 nsec maximum channel to channel and module to module.

Temperature Coefficient:

Typically 100 psec/'C.

Range:

300-750 nsec in two jumper-selectable ranges: 300-682.5 nsec and 330-750 nsec.

Programming:

8 bits, 1.5 or 1.65 nsec jumper selectable) nsec steps. Set via the Model 2738. Separate delay register per 2731A module.

Double Pulse Resolution:

100 nsec typically. 150 nsec maximum.

Delay 16:

One front-panel output. Provides channel 16 logic signal of amplitude ~=5 mV after the Ripplethru delay. Used to check approximate Ripplethru delay. Must be terminated in 50 Q for correct output pulse shape. May be unter- minated when not in use.

Internal Delay:

500 kHz front-panel signal with low level width equal to the delay setting. Amplitude approximately 25 mV in to 50 ohm.

THRESHOLD CONTROL

Threshold Programming:

8 bits,0.06 uA steps when used with the 2735 Series. Set via the Mode 12738. Separate threshold register per 2731A module. Programming level and ground applied to the chamber cards via a single pair of pins on each of the signal input headers. Pin 33 is ground and Pin 34 is the programmed level.

Threshold Monitor:

A2-pin header labeled THR on the front panel. Provides a level of 0.5 V/uA when used with 2735 Series Chamber Card.

Threshold Polarity Select:

Internal wire-wrap option. Factory wired positive.

OUTPUTS

OR Outputs:

16 differential ECL outputs. Internal wire wrap options allow prompt or latched OR signal (1 to 32-fold)to be con- nected to any of the OR outputs.

Prompt OR Outputs:

32 open-collector OR signals preceeding the Ripplethru delay. Available on wire wrap posts within the Model 2731A. May be arbitrarily wired OR'd to the 16-position internal options connector. Signals are approximately equal to the input width plus 35 nsec. Availble within 30 nsec of the input.

Auxiliary Latched OR Outputs:

Thirty-two open-collector OR signals representing the status of each of the 32 latches. Availble on wire wrap posts within the Model 2731A. May be arbitrarily wired OR'd to the 16-position internal options connector. Levels are valid within 30 nsec of the trailing edge of the coincidence gate.

GENERAL

Controls:

Leftmost module must have termination of all control lines. Termination via two 8-pin SIP resistor arrays. All modules shipped with SIP's installed. See cut in the side panel for location.

Power Requirements:

<950 mA at + 6 V
<900 mA at - 6 V
<210 mA at + 24 V
< 20 mA at - 24 V

If prompt and latched OR's are not required, ECL drivers may be removed, saving 400 mA at - 6 V and 70 mA at + 6 V.

Packaging:

In conformance with CAMAC standard for nuclear modules (ESONE Committee Report EUR4100e). RF shielded CAMAC #1 module.

Caution:

Power up this module when a PCOS III System Controller Model 2738, is in the controller position.

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INPUTS
IN A, IN B:	32 differential ECL inputs via two 17-pair front-panel headers. Input impedance 112 +/-2ohm. input configuration com- patible with LeCroy ECLine logic standard. Minimum pulse width 10 nsec.
Coincidence Gate:	Two differential ECL inputs applied from the Model 2738 via the CAMAC connector. Board-mounted jumper selects input El or input E2. Minimum width 30 nsec.
Test Input:	Two differential ECL inputs applied from the Model 2738 via the CAMAC connector Board mounted jumper selects input E3 or input E4. Minimum width 6O nsec. Applies a test input via the 32 pattern gates to the Ripplethru inputs. Test level must be logical "zerd" for data acquisition. Model 2731A should be inhibited during Test.
Clear:	Applied by the 2738 via CAMAC Dataway. Transmitted as an ECL pulse. Clears all latches within 30 nsec. Minimum width 100 nsec.
Inhibit:	Applied by the 2738 via the CAMAC Dataway. Common inhibit line set via programmable bit in the 2738 disables all 32 ECL inputs. Should be set when applying Test pulse.
RIPPLETHRU DELAY CIRCUIT
Delay Variations:	+/- 5 nsec typical, +/- 10 nsec maximum channel to channel and module to module.
Temperature Coefficient:	Typically 100 psec/'C.
Range:	300-750 nsec in two jumper-selectable ranges: 300-682.5 nsec and 330-750 nsec.
Programming:	8 bits, 1.5 or 1.65 nsec jumper selectable) nsec steps. Set via the Model 2738. Separate delay register per 2731A module.
Double Pulse Resolution:	100 nsec typically. 150 nsec maximum.
Delay 16:	One front-panel output. Provides channel 16 logic signal of amplitude ~=5 mV after the Ripplethru delay. Used to check approximate Ripplethru delay. Must be terminated in 50 Q for correct output pulse shape. May be unter- minated when not in use.
Internal Delay:	500 kHz front-panel signal with low level width equal to the delay setting. Amplitude approximately 25 mV in to 50 ohm.
THRESHOLD CONTROL
Threshold Programming:	8 bits,0.06 uA steps when used with the 2735 Series. Set via the Mode 12738. Separate threshold register per 2731A module. Programming level and ground applied to the chamber cards via a single pair of pins on each of the signal input headers. Pin 33 is ground and Pin 34 is the programmed level.
Threshold Monitor:	A2-pin header labeled THR on the front panel. Provides a level of 0.5 V/uA when used with 2735 Series Chamber Card.
Threshold Polarity Select:	Internal wire-wrap option. Factory wired positive.
OUTPUTS
OR Outputs:	16 differential ECL outputs. Internal wire wrap options allow prompt or latched OR signal (1 to 32-fold)to be con- nected to any of the OR outputs.
Prompt OR Outputs:	32 open-collector OR signals preceeding the Ripplethru delay. Available on wire wrap posts within the Model 2731A. May be arbitrarily wired OR'd to the 16-position internal options connector. Signals are approximately equal to the input width plus 35 nsec. Availble within 30 nsec of the input.
Auxiliary Latched OR Outputs:	Thirty-two open-collector OR signals representing the status of each of the 32 latches. Availble on wire wrap posts within the Model 2731A. May be arbitrarily wired OR'd to the 16-position internal options connector. Levels are valid within 30 nsec of the trailing edge of the coincidence gate.
GENERAL
Controls:	Leftmost module must have termination of all control lines. Termination via two 8-pin SIP resistor arrays. All modules shipped with SIP's installed. See cut in the side panel for location.
Power Requirements:	<950 mA at + 6 V <900 mA at - 6 V <210 mA at + 24 V < 20 mA at - 24 V If prompt and latched OR's are not required, ECL drivers may be removed, saving 400 mA at - 6 V and 70 mA at + 6 V.
Packaging:	In conformance with CAMAC standard for nuclear modules (ESONE Committee Report EUR4100e). RF shielded CAMAC #1 module.
Caution:	Power up this module when a PCOS III System Controller Model 2738, is in the controller position.