LeCroy 4299 Databus Interface

CAMAC Model 4299 Databus Interface

The LeCroy 4299 is a single-width CAMAC interface and data buffer designed for use with LeCroy's expanding family of dedicated CAMAC crate data acquisition systems. These include System 4290, PCOS III, and others. The Model 4299 allows connecting of up to 16 dedicated crates to a single CAMAC station.

The LeCroy DATABUS connects the 4299 with System Controllers (4298, 2738, etc.). This is a bi- directional 16-bit ribbon cable bus. It allows data to be read from LeCroy dedicated crate systems and test or control information to be downloaded to the crates.

The system includes a 4k X 16-bit memory. This allows blocks of data to be transferred to the 4299. Block transfer is ideal for applications which require rapid readout. It may also be operated in the Word Step mode. Data words may be transferred one at a time under CAMAC control.

The Model 4299 has been designed with maximum flexibility for readout of data acquisition systems. The Model 4299 offers destructive or non-destructive readout. It also offers a word count register to facilitate block transfer readout. Side panel accessed switches enable memory overwrite protection from either the Dataway or the DATABUS. Thus, the 4299 may be used as a multiple-event buffer or as a single-event buffer. Front panel Lemo-type connectors allow the user to reset or clear the 4299 with NIM pulses.

A register internal to the Model 4299 can be set by any dedicated controller in the DATABUS chain. This sets the LAM of the Model 4299 and lights a front panel LED labeled LR. The LAM status of the 4299 can be tested or cleared by standard CAMAC commands. It can also be cleared via the front panel Reset or Clear Lemo inputs provided that none of the System Controllers are asserting the LAM.

The operating mode of the LAM circuit can be selected via a side-panel switch, CLEAR LAM. The CLEAR LAM switch has the following four positions:

LMD: The LAM memory circuit is disabled. Reset is possible via dedicated crate controller only.

FWR: LAM is reset at the end of the first readout cycle, FR, or by any of the valid clear functions.

LWR: LAM is reset at the end of the last readout cycle, FR, or by any one of the valid clear functions.

DRC: LAM is not automatically reset by the readout function, FR. All other clear functions remain valid.

SPECIFICATIONS CAMAC Model 4299 DATABUS INTERFACE BUFFER

INPUTS

General:

Front panel connectors, LEMO type.

Impedance:

50 Ohm +/- 5%. Direct coupled. Requires NIM-level signal.

Reset (RT):

One; resets all registers and memory. Minimum width: 20 nsec.

Clear (CL):

One; clears memory only. Minimum width: 50 nsec.

OUTPUTS

General:

Front-panel connectors, LEMO type. High impedance current source. Bridge outputs. NIM levels into 25 Ohm; 0 level = 0 mA +/- 4 mA; 1 level = 32 mA +/- 4 mA. Risetimes and falltimes: < 5 nsec, overshoot: 10%.

Memory Busy (MB):

Memory Busy signal; indicates that the memory contains data or is being accessed.

DATABUS Busy (DB):

DATABUS Busy signal; indicates that the DATABUS BUSY is activated.

CAMAC COMMANDS

C S2:

Memory clear (jumper option).

Z S2:

Clears memory, initializes logic status of the unit and generates initialize cycle on the DATABUS.

I:

Activates DATABUS Inhibit line. Front-panel INH LED indicates status.

L:

LAM signal is activated by DATABUS LR request. A front-panel LR LED indicates status.

X:

An X-response is generated when any valid N A F command below is recognized even though it may not be executed.

Q:

A Q-response is generated only if the request function can be executed.

N F(R) A(0):

Memory destructive READ function. Can be chosen among CAMAC functions F(0), F(1), F(2) or F(3). Q-response generated if function is executed.

N F(R) A(1):

Memory non-destructive READ function. Can be chosen among CAMAC functions F(0), F(1), F(2) or F(3). Q-response generated if function is executed.

N- F(8) [A(0) + A(1)]:

Tests LAM. Q-response generated only if LAM is present.

N F(9) [A(0) + A(1)]:

Clears memory, initializes logic status of the unit, and generates initialize cycle on the DATABUS. Q-response generated.

N- F(11)-A(0):

Clears memory. Q-response generated if memory not activated by the DATABUS.

N F(11)-A(1):

Initialize memory address counter for a new readout cycle. Q-response generated if memory not activated by the DATABUS.

N F(W) A(0):

DATABUS WRITE function. Can be chosen among. CAMAC functions F(16), F(17), F(18) or F(19) to write one word at a time on the DATABUS. Q-response generated if function is executed.

N- F(W)-A(1):

Memory WRITE function. Can be chosen among CAMAC functions F(16), F(17), F(18) or F(19). Q-response generated if function is executed.

N-F(24) [A(0)+ A(1)]:

Sets DATABUS Inhibit. Q-response generated.

N F(25) [A(0)+ A(1)]:

Triggers the transfer of memory data onto the DATABUS. Q-response generated if data transfer is executed.

N- F(26) [A(0) + A(1)]:

Resets DATABUS Inhibit. Q-response generated.

N F(27)-[A(0)+ A(1)]:

Tests DATABUS BUSY signal. Q-response generated if DATABUS BUSY signal is pre- sent.

R1 to R16:

Data read lines.

W1 to W16:

Data write lines.

PACKAGING

No. 1 RF-shielded CAMAC module conforming to ESONE Report EUR4100e and IEEE Standard 583.

CURRENT REQUIREMENTS

+ 6 V at 2A;
6 V at 200 mA.

Up to a higher level directory | | For more information

INPUTS
General:	Front panel connectors, LEMO type.
Impedance:	50 Ohm +/- 5%. Direct coupled. Requires NIM-level signal.
Reset (RT):	One; resets all registers and memory. Minimum width: 20 nsec.
Clear (CL):	One; clears memory only. Minimum width: 50 nsec.
OUTPUTS
General:	Front-panel connectors, LEMO type. High impedance current source. Bridge outputs. NIM levels into 25 Ohm; 0 level = 0 mA +/- 4 mA; 1 level = 32 mA +/- 4 mA. Risetimes and falltimes: < 5 nsec, overshoot: 10%.
Memory Busy (MB):	Memory Busy signal; indicates that the memory contains data or is being accessed.
DATABUS Busy (DB):	DATABUS Busy signal; indicates that the DATABUS BUSY is activated.
CAMAC COMMANDS
C S2:	Memory clear (jumper option).
Z S2:	Clears memory, initializes logic status of the unit and generates initialize cycle on the DATABUS.
I:	Activates DATABUS Inhibit line. Front-panel INH LED indicates status.
L:	LAM signal is activated by DATABUS LR request. A front-panel LR LED indicates status.
X:	An X-response is generated when any valid N A F command below is recognized even though it may not be executed.
Q:	A Q-response is generated only if the request function can be executed.
N F(R) A(0):	Memory destructive READ function. Can be chosen among CAMAC functions F(0), F(1), F(2) or F(3). Q-response generated if function is executed.
N F(R) A(1):	Memory non-destructive READ function. Can be chosen among CAMAC functions F(0), F(1), F(2) or F(3). Q-response generated if function is executed.
N- F(8) [A(0) + A(1)]:	Tests LAM. Q-response generated only if LAM is present.
N F(9) [A(0) + A(1)]:	Clears memory, initializes logic status of the unit, and generates initialize cycle on the DATABUS. Q-response generated.
N- F(11)-A(0):	Clears memory. Q-response generated if memory not activated by the DATABUS.
N F(11)-A(1):	Initialize memory address counter for a new readout cycle. Q-response generated if memory not activated by the DATABUS.
N F(W) A(0):	DATABUS WRITE function. Can be chosen among. CAMAC functions F(16), F(17), F(18) or F(19) to write one word at a time on the DATABUS. Q-response generated if function is executed.
N- F(W)-A(1):	Memory WRITE function. Can be chosen among CAMAC functions F(16), F(17), F(18) or F(19). Q-response generated if function is executed.
N-F(24) [A(0)+ A(1)]:	Sets DATABUS Inhibit. Q-response generated.
N F(25) [A(0)+ A(1)]:	Triggers the transfer of memory data onto the DATABUS. Q-response generated if data transfer is executed.
N- F(26) [A(0) + A(1)]:	Resets DATABUS Inhibit. Q-response generated.
N F(27)-[A(0)+ A(1)]:	Tests DATABUS BUSY signal. Q-response generated if DATABUS BUSY signal is pre- sent.
R1 to R16:	Data read lines.
W1 to W16:	Data write lines.
PACKAGING	No. 1 RF-shielded CAMAC module conforming to ESONE Report EUR4100e and IEEE Standard 583.
CURRENT REQUIREMENTS	+ 6 V at 2A; 6 V at 200 mA.