The LeCroy Model 4300 Fast Encoding and Readout ADC (FERA) is designed to cover applications where charge measurements and readout must be performed rapidly and with high resolution. The FERA may be used as a single standard CAMAC module, or as part of a large system.
The FERA is a high speed charge integrating analog-to-digital converter. Each module contains 16 independent ADCs that are enabled by a common gate of 50 nsec to 500 nsec duration. Larger gate widths are possible after pedestal adjustment. The inputs, designed to accommodate 17 pair flat cables, offer common mode rejection of +/- 200 mV.
After conversion, the digitized data may be automatically corrected for pedestal with values contained in the internal programmable pedestal memory. Digitized data is available first on the front panel ECL port and, subsequently, on the CAMAC dataway. The ECL port readout may be suppressed. All zero data words may be suppressed separately for ECL port or CAMAC readout to provide data compression. The compression procedure requires 1.6 usec (both after the conversion and ECL port readout).
The front panel bus system includes the protocol necessary to permit high speed sequential readout to ECLine compatible modules including LeCroy Models 2374 Data Stack Module, 2372 Memory Lookup Unit, and 4302 Triple Port Fast Memory. The Model 4302 is the memory extension of the LeCroy 4800 series of Fast Bit Slice CAMAC Processors which permits the distribution of programmable intelligence within the CAMAC system.
Control, testing, readout modes and pedestals are under complete CAMAC control. The Model 4301 FERA Driver, when used in conjunction with several 4300 modules, permits simple distribution of all control signals including the gate, fast clear, test and ECL port readout handshake.
SPECIFICATIONS CAMAC Model 4300 16 CHANNEL, FAST ENCODING AND READOUT ADC (FERA) ANALOG INPUTS (16) Connector: 17 x 2-pin front panel connector (BERG 75789-101-34). The upper 16 pins of the left row are negative signal inputs. The upper 16 pins of the right row are connected to the common virtual ground (AC coupled to ground). The lowest 2 pins are connected to ground. Input Sensing: Charge (current integrating). Full Scale: 256 pC (9 or 10 bits), 480 pC (11 bits). ADC Resolution: Two factory options: 9 bits or 10/11 bits; the 10/11-bit selection is made via 4 internal jumpers and adjustment by an internal potentiometer. Conversion Time: Typically 9 bits in 2.8 usec, 10 bits in 4.8 usec, 11 bits in 8.5 usec. Range: 9 or 10 bits typically 256 pC minus ADC pedestal. 11 bits typically 480 pC minus ADC pedestal. Sensitivity: 10 or 11 bits 0.25 pc/count + 3%, 9 bits 0.5 pc/count + 3%. Input Impedance: Two factory options: 100 Ohm +/- 3%, within the range of 0 to -30 mA DC; or 50 Ohm +/- 3%, within the range of 0 to -60 mA DC. Above these limits, diode protection clamping will affect input impedance. Input Protection: + 25 V for 1 usec transients (clamping diodes to ground and -3 V). Input Limitations: Maximum current for linear response -30 mA. With 50 input impedance, the linearity is degraded to typically +/- (1% of reading + 0.25 pC) for -60 mA. Common Mode Properties: Common mode rejection ratio > 50 dB for +/- 200 mV (DC to 1 kHz). ADC Isolation: > 50 dB. Integral Linearity: Typically + 0.5 pC. Worst case + (0.25% of reading + 0.5 pC) for signals of slew rate < 2 mA/nsec. For signals of slew rate 4 mA/nsec, linearity is degraded to typically +/-(1% of reading + 0.25 pC). Differential Linearity: Typically +/- 0.25 LSB, worst case +/- 0.5 LSB. Residual Pedestal: Minimum 1 pC and maximum 13 pC for a gate width from 50 to 500 nsec and all inputs open. Adjustable with an internal potentiometer for gate width > 500 nsec. Subtracted from data by CAMAC command. Pedestal/Gate Width Coefficient: < + 8 pC/usec, typically +/- 3 pC/usec. Operating 0 0 Temperature: 0 to 40 C. Temperature Coefficient: Typically (-0.05% of reading +/- 0.1 count)/'C for a gate width of 500 nsec. Coefficient may vary slightly for other gate widths. Long Term Stability: + (0.25% of reading + 0.5 pc)/week at constant temperature and voltage. COMMAND BUS Connector: 8 x 2-pin front panel connector. The input matching resistors and output pull down resistors may be removed for high impedance inputs and outputs. When these resistors are in place, a front panel LED (PD ON) is lit. Input Levels: Differential ECL levels, 100 Ohm impedance differential. Output Levels: Differential ECL levels (into 100 Ohm differential). Gate Input (GATE): One, common for all ADCs. Non-retriggerable. Gate width 50 to 500 nsec (> 500 is possible after pedestal adjustment). Gate must precede input signals by at least 20 nsec. Clear Input (CLR): One, common for all ADC front ends and digital logic. May be executed at any time. Minimum clear width: 5 nsec. CLEAR settles to within 1 count in less than 2 usec during conversion, the action is immediate after conversion. Request Output (REQ): One, ECL port readout request indicates that this module is ready to take control of ECL port data transfer. After conversion time, REQ is set only if the ECL port readout is programmed and the module contains valid data. Write Strobe Output (WST): One, indicates when the data is valid on the ECL port output. WST is set a minimum of 10 nsec after the data is presented to the ECL port (settling time) and released when the write acknowledge is received. The ECL port data is stable during entire WST pulse. Minimum write strobe width 40 nsec. Write Acknowledge Input (WAK): One, acknowledge signal from the ECL port receiver indicating data has been loaded and the next data word may be sent. The next WST is set 50 nsec after the release of WAK. Minimum write acknowledge width 30 nsec. Test Reference Voltage Input (TRV): Two paralleled front panel 2-pin connectors, high input impedance (200 KOhm), accept the Test Reference Voltage; second connector usable for monitoring or daisy chaining. The gate and charge pulses are generated at the input of all ADCs by the CAMAC function F(25)-A(O). The test charge pulse is proportional to the DC level at the TRV input. Channel-to-channel matching of the proportionality constant is + 1%. TRV input range: 0 to + 10.24 V, equivalent to 0 to 512 pC + 0.1% on each ADC. The common virtual ground offset is automatically compensated. ENABLE/PASS READOUT COMMAND Readout Enable Input (REN): 1 x 2-pin front panel connector. Accepts dif f erential ECL levels. Input impedance 100 ii differential. Indicates to this module that it can take control of the ECL Port Bus. The REN signal must be maintained during entire readout time. REN enables the ECL port outputs, WST output and WAK input if the module is ready for data transfer (REQ output ON). Pass Output (PASS): 1 x 2-pin front panel connector, generates differential ECL levels (into 100 Ohm differential). Indicates that this module has finished using the ECL port or is not ready. PASS output is activated by the REN input signal and closed by the REQ output internal command. Transit time between REN input and PASS output typically 3 nsec if module empty. ECL PORT OUTPUT Connector: 17 x 2-pin front panel connector; (BERG 75789-101-34). The last 2 pins are not connected. Output Levels: Differential ECL levels (into 100 Ohm differential). The pull down resistors may be removed for high impedance outputs. When these resistors are in place, a front panel LED (PD ON) is lit. Specifications: Data word size: 16 bits. Sequential data readout with maximum output frequency 10 MHz (see Readout Block Size). CAMAC COMMANDS Note: after a GATE the module is BUSY (=1), and only the data readout functions are enabled. The BUSY status is released (=O), only after a clear CAMAC function or front panel CLR signal. Z: Initializes module; clears the module and sets the seven command bits of the status register to 1. C: Clears the module. Inhibits the front panel GATE during CAMAC inhibit command. X: X response is generated for all valid functions. Q: Q response is generated only if a function can be executed. L: Look-At-Me (LAM) set after the end of conversion or ECL port readout provided that is enabled (CLE = 1) and there is valid data to be read from the module. LAM is cleared by Z, C, F(9), F(10), front panel CLR or, if sequential read is selected, by F(2) after the last data has been read. F(0)-A(0): Read status word register. Rl to R15; R16 = 0; Q = 1 if BUSY = 0. Rl to R8: VSN; Virtual Station Number: index source for sequential readout with zero suppression. R9: EPS; ECL port Pedestal Subtraction: when EPS = 1, pedestals are subtracted for ECL port readout. R10: ECE; ECL port data Compression Enable: when ECE = 1, data zeros are suppressed for ECL port readout. Rll: EEN; ECL port ENable: when EEN = 1, ECL port readout is permitted. R12: CPS; CAMAC Pedestal Subtraction: when CPS = 1, pedestals are subtracted for CAMAC readout. R13: CCE; CAMAC data Compression Enable: when CCE = 1, data zeros are suppressed for CAMAC sequential readout. R14: CSR; CAMAC Sequential Readout: when CSR = 0, CAMAC random access readout is enabled; when CSR = 1, CAMAC sequential readout is enabled. R15: CLE; CAMAC LAM Enable: when CLE = 1, LAM is enabled. Note: The seven bits, EPS to CLE, are set to 1 by the CAMAC Z function. F(l)-A(0-15): Reads pedestal memory on Rl to R8; R9 to R16 = 0. Random access to the 16 pedestal words. Channels 0 to 15 are addressed by subaddresses as 0-15. Q = 1 if BUSY = 0. F(2)-A(0-15): CSR = 0; random access to the 16 ADC values. Reads ADC value on Rl to Rll; R12 to R16 = 0. Channels 0 to 15 are addressed by subaddresses 0-15. Q = 1 if BUSY = 1 and provided data are ready. F(2)-A(0-15): CSR = 1; sequential readout of ADC values. Reads ADC value on Rl to R16 (see Readout Block Size). Increment to the next word is triggered by S2. Q = 1 if BUSY = 1 and as long as valid data to be read are present. The subaddress A is not decoded. F(8)-A(0): Tests Look-At-Me. Q = 1 if LAM is present. F(9)-A(0): Clears the module. Q = 1. F(10)-A(0): Tests and clears LAM. Q = 1 if LAM is present; LAM reset at S2 if set. F(16)-A(0): Writes status word register. Wl to W15; W16 not used (see F(0) for assignment). Q = 1 if BUSY = 0. The status word register is loaded at Sl. F(17)-A(0-15): Random access for writing of the 16 pedestals. Writes pedestal memory on Wl to W8; W9 to W16 not used. Channels 0 to 15 are addressed by subaddress 0-15. Q = 1 if BUSY = 0. The 8-bit pedestal word is loaded at Sl. F(25)-A(0): Enables test. Q 1 if BUSY = 0. At S2 the gate opens for 550 nsec and generates a charge, proportional to the TRV applied on the TRV input, to each ADC. Maximum rate 10 kHz; recovery time 100 usec.
Factory Input/Resolution Options
| Input Z | MOD | Resolution | Conv. Time | Full Scale | Sensitivity | Digital Values | |
| FS | OF | ||||||
| 100 | 100 | 8 Bit | 1.8uSec | 128pC | .05pC/Count | 255 | 2047 |
| 50 | 500 | ||||||
| 100 | 110 | 9 Bit | 2.8uSec | 256pC | 0.5pC/Count | 511 | 2047 |
| 50 | 510 | ||||||
| 100 | 200 | 10 Bit | 4.8uSec | 256pC | 0.25pC/Count | 1023 | 2047 |
| 50 | 600 | ||||||
| 100 | 210 | 11 Bit | 8.5uSec | 480pC | 0.25pC/Count | 1919 | 2047 |
| 50 | 610 | ||||||