The Model 4301 Fast Encoding and Readout ADC System Driver provides a simple mechanism for the distribution and collection of common signals for up to an entire crate of Model 4300 FERAS. The functions include all ADC control functions such as Gate and Clear as well as all timing and control functions for the ECL Port.
An internal CAMAC controlled Digital-to-Analog Converter (DAC) permits precise generation of reference voltage levels for test and calibration of the Model 4300 FERAS.
The Model 4300 FERAs use an ECL Port for 10 MHz readout of the 16-bit data words. When bussed together, these standard differential ECL signals become single-ended ECL. The signals must be converted back to differential ECL before being sent to a standard ECLine logic module or memory unit. This translation is conveniently handled by the Model 4301. Connectors are located at the same position as those for the Model 4300 ECL Port and the Model 4302 Triple Port Fast Memory Module to permit simple interconnections.
The Model 4301 FERA Driver uses two separate ECL Busses. The Command ECL Bus is used to receive and distribute signals used by a set of FERAs via an 8 x 2-pin connector. The Data ECL Bus is connected to the ECL Ports of the Model 4300 FERAs and carries the data during fast readout. The Data ECL Bus uses a standard ECLine 17 x 2-pin connector for both input and output interconnections. Let--roy recommends one Model 4301 be used with up to 22 Model 4300 FERAS, a full CAMAC crate.
INPUT/OUTPUT CHARACTERISTICS
Gate (GAI & GATE): Two inputs (GAI); Lemo-type connector accepts NIM signal levels (50 Ohm input impedance), and 1 x 2-pin connector accepts differential ECL signals (100 Ohm input impedance). Inputs are OR'd and available on the Command ECL Bus (GATE) for distribution to the Model 4300 FERAS. Clear (CLI & CLR): Two inputs (CLI); Lemo-type connector accepts NIM signal levels (50 Ohm input impedance), and 1 x 2-pin connector accepts differential ECL signals (100 Ohm input impedance). Inputs are OR'd and available on the Command ECL Bus (CLR) for distribution to the Model 4300 FERAS. Write Acknowledge (WAI & WAK): Two inputs (WAI); Lemo-type connector accepts NIM signal levels (50 Ohm input impedance), and 1 x 2-pin connector accepts differential ECL signals (100 Ohm input impedance). Inputs are OR'd and available on the Command ECL Bus (WAK) for distribution to the Model 4300 FERAS. The WAK may also echo the WST signal after a fixed time delay as described below. Write Strobe (WST & WSO): Input via Command ECL Bus (WST) from the Model 4300 FERAs. Two Outputs (WSO); Lemo-type connector generates NIM signal levels into 50 Ohm impedance, and 1 x 2-pin connector generates differential ECL signals into 100 Ohm For synchronous operation, the WSO signal may be connected directly to the WAI via a fixed delay cable or active delay. Inhibit Readout (IRI): Two inputs (IRI); Lemo-type connector accepts NIM signal levels (50 Ohm input impedance), and 1 x 2-pin connector accepts differential ECL signals (100 Ohm input impedance). Inputs are OR'd and act as a veto for the REO signal described below. Since the REO is usually connected to the first Model 4300 FERA to be read out, the IRI inhibits the readout and may be used to block the readout process until the receiver module is ready. Readout Request (REQ, RQO & REO): Input via Command ECL Bus (REQ) from the Model 4300 FERAs. Following a fixed delay, three ouputs are generated (factory setting for delay, 200 nsec; may be adjusted by internal potentiometer RQ DEL). The first two outputs (RQO) may be used to signal a request to readout; Lemo-type connector generates NIM signal levels into 50 Ohm impedance, and 1 X 2-pin connector generates differential ECL signals into 100 a The third output (REO) can be vetoed by the IRI signal and is normnally connected to the REN or Readout Enabled input of the first Model 4300 FERA to be read out; 1 x 2-pin connector generates differential ECL signals into 100 Ohm Test Reference Voltage (TRV): Internal CAMAC controlled 12-bit DAC generates a precision reference voltage on the Command ECL Bus (TRV), for testing and calibrating the Model 4300 FERAs (see complete description below). ECL Data Bus (IN & OUT): 16 inputs via 17 x 2-pin connector (IN). Accepts single ended ECL signals from the ECL Ports of the Model 4300 FERAs. Generates differential ECL ouputs on the 17 x 2-pin connector (OUT) for all 16 signals. TEST REFERENCE VOLTAGE SPECIFICATIONS The TRV output on the Command ECL Bus is driven by an internal CAMAC controlled Digital-to-Analog Converter (DAC). The DAC uses a control register which may be set and read via CAMAC commands (see below). WARNING: the register content is randomly set at power on. Range: 0 to 10.2375 V corresponding to inputs for the Model 4300 FERA of 0 to 511.875 pC. LSB: 2.5 mV corresponding to inputs for the Model 4300 FERA of 0.125 pC. Integral Linearity: +/- 0.5 LSB. Full Scale Error: +/- 1 LSB. Settling Time: 5 usec. Current Limit: 3 mA. CAMAC COMMANDS X, Q: X and Q responses are generated for each valid function. F(O)-A(O): Read the contents of the 12-bit DAC control register on CAMAC lines R1 to R12. X and Q responses are generated. F(9)-A(O): Generate a CLR signal on the Command ECL Bus at time S1. Same action as front panel CLI input. X and Q responses are generated. F (I 6)-A(O): Set the contents of the 12-bit DAC control register from CAMAC lines W1 to W12. X and Q responses are generated. GENERAL Packaging: Single-width CAMAC module. Current Requirements: 20 mA at +24 V 100 mA at +6 V 1.2 A at -6 V 30 mA at -24 V