LeCroy 4302 Fast Memory Unit

CAMAC ECLine Model 4302 Triple Port Fast Memory Unit

* Fast Access Time: 100 nsec.
* Large Size: 16K by 16-bits.
* Two Read/Write Ports and One Write Port.
* Compatible with FERA, the LeCroy Fast Encoding and Readout ADC System.
* Compatible with PCOS III, the LeCroy multiwire Proportional Chamber System.
* May be used to Expand the Memory of the LeCroy Series 4800 CAB Programmable CAMAC Processors.

The LeCroy Model 4302 Triple Port Fast Memory Unit has been designed for a variety of appli- cations requiring large fast buffer memories. A large fast access time buffer memory may be used to liberate front-end electronics in high data rate applications. Several events may be accumulated in the buffer for subsequent readout and processing.

With a 100 nsec access time to the 16K by 16-bit memory, the Model 4302 is fast enough to be a complement to ECLine, the fast pulse CAMAC programmable logic system from LeCroy. The flexibility of the module is further enhanced by the Model 4302s three ports. The memory unit has a read/ write port to CAMAC, a read/write port to the LeCroy 4800 series of fast intelligent CAMAC processors (CAB), and, finally, a fast ECL write port on the front panel for rapid data loading. Several 4302 modules may be cascaded to extend the memory capacity to multiples of 16K.

Data loaded into the Model 4302 Memory Unit may be accessed either by CAMAC or directly by a LeCroy Series 4800 CAB Programmable CAMAC Processor. The Model 4302 can be directly connected to the CAB via the CAB internal bus and data is available within the indirect address space of the processor. Up to four Memory Units can be directly coupled to the CAB for a total of 64K 16-bit words.

Atypical application of the Model 4302 is with one or more LeCroy Model 4300 Fast Encoding and Readout ADCs (FERA) accessing the Model 4302 Memory Units via their front panel ECL Ports.

SPECIFICATIONS CAMAC ECLine Model 4302 TRIPLE PORT FAST MEMORY UNIT

INPUT CHARACTERISTICS

Data Inputs:

Front panel, 34-pin connector accepts complementary ECL signals; 1 00 Ohm input impedance; up to 16 parallel bits can be accepted and stored in the memory word addressed at the strobe pulse arrival time; memory address is automatically incremented by one at the end of the strobe pulse.

Strobe Veto (VETO):

Front panel, 2-pin connector accepts complementary ECL pulses. 1 00 input impedance; an input signal acts as a veto on the Write Strobe Input (WSI).
Connecting the FULL output on the VETO input in adjacent Model 4302 permits simple cascading of memory units. WSI and Data Inputs must also be connected.

Write Strobe (WSI):

NIM: two bridged Lemo-type connectors, high input impedance, accepts NIM level pulses; unused input must be terminated. ECL: front panel, 2-pin connector accepts complementary ECL pulses; 100 Ohm input impedance.
The leading edge of the strobe pulse must fall inside the data pulse and must arrive at least 10 nsec after the data are valid; minimum width 20 nsec; maximum frequency 10 MHz for both NIM and ECL.

Clear Address Counter (CLR):

NIM: Lemo-type connector, input impedance 50 Ohm, minimum pulse width 20 nsec, accepts NIM level pulses; an input pulse resets the memory address and clears the LAM.

OUTPUT CHARACTERISTICS

Overflow (OVF):

NIM: Lemo-type connector; generates NIM level pulses when ter- minated in 50 Ohm.

ECL: front panel, 2-pin connector generates complementary ECL levels. When the ECL port is enabled, a signal is generated as long as the memory address is equal to or exceeds the value that has been preset by switches on the side of the module; the output is active until the memory address is changed (either by the CAB or by CAMAC). The two side panel switches permit the selection of 12288,14336,15360, or 15872 as the overflow address.

Acknowledge (ACK):

ECL: front panel 2-pin connector, generates a complementary ECL signal; echoes WSI with 35 nsec delay time; inhibited if the address counter has reached full memory capacity.

Memory Full (FULL):

ECL: front panel 2-pin connector, generates a complementary ECL level; active as long as the address counter has not reached the full memory capacity.

CAB COMMANDS AND FUNCTIONS

G I(2)-I(5):

Sets operation mode in the addressed memory.
I(5),I(4) =2-bit memory address.
I(3),I(2)= mode:
00 = no action;
01 = enable CAMAC, disable CAB and ECL port;
10 = enable CAB, disable CAMAC and ECL port;
11 = enable ECL port, disable CAMAC and CAB;
This general function may be executed at any time.

TxW0:

Writes address pointer.

TxW1:

Writes a 16-bit data word into the actual address and increments address by one.

TW0x i:

Reads address pointer, where i = 0, 1, 2, 3 is the address of the memory unit.

TW1 x:

Reads a 16-bit data word out of the actual address and increments address by one.

Note: The transfer instructions yield valid results only when in CAB operation mode.
x = any source of destination register on the CAB data bus.

CAMAC COMMANDS AND FUNCTIONS

A LAM is generated on overflow (OVF).

Resets memory address to zero and clears the LAM.

X = 1 response is generated for each valid CAMAC function.

Q = 1 response is generated for any executable function unless other- wise specified.

F(0)-A(0):

Reads 16-bit data at the current memory address; increments the address by one at S2. No Q response is generated when the address pointer exceeds the memory capacity.

F(1)-A(0):

Reads memory address on 16 bits (R1 to R16). The presence of the two most significant bits indicates memory address overflow.

F(1)-A(1):

Reads mode register (CAMAC Read Lines R1 and R2).

R2	R1
0	1	CAMAC Enabled
1	0	CAB Enabled
1	1	ECL Enabled

F(2)-A(0):

Reads 16-bit data at the current memory address and decrements the address pointer by one at S2. The first F(2)-A(0) reads the address pointer. The Q response is suppressed on further F(2)-A(0) reads after the data word at address 0 has been read.

F(8)-A(0):

Tests LAM.

F(10)-A(0):

Tests and clears LAM.

F(16)-A(0):

Writes 16-bit data at the current memory address; increments the address by one at the end of S1. No Q response when the pointer exceeds the memory capacity.

F(17)-A(0):

Writes memory address on 14 bits (W1 to W14).

F(17)-A(1):

Writes mode register (CAMAC Write Lines Wl and W2).

W2	W1
0	0	Disables all modes
0	1	Enables CAMAC
1	0	Enables CAB
1	1	Enables ECL

F(24)-A(0):

Disables LAM.

F(26)-A(0):

Enables LAM. LAM is generated on overflow.

F(0)-A(0), F(1)-A(0), F(2)-A(0), F(16)-A(0), and F(17)-A(0) cannot be executed and no Q response is generated unless the unit is in CAMAC operation mode.

GENERAL

Packaging:

RF-shielded, # 1 width CAMAC module.

Power requirements:

2.2 A at +6 V;
200 mA at -6 V.

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