LeCroy Model 4432 GENERAL DESCRIPTION
LeCroy Model 4432 GENERAL DESCRIPTION
The LeCroy Model 4432 offers, in a one unit wide CAMAC module, 32 x 24 bit latching scalers.
This unit represents a great improvement over all existing scalers in terms of channel density and overall cost per channel.
The scaler accepts either differential ECL or TTL single ended input signals (the last,option selectable) and the three front panel control signals (LOAD/CLEAR/VETO) may be either NIM or TTL.
The maximum continuous input counting frequency is > 20 MHz.
Figure 1 shows the general block diagram of the unit; the first stage of each scaler is integrated in a new hybrid circuit containing the 8 least signi- ficant bits counters and 3 -state output latches.
A fast bipolar random access memory is used to hold the 16 M.S.B. of all 32 scalers; that memory is scanned continuously and each memory location, al- located to one of the 32 scalers, is incremented when the hybrid prescaler has made a full turn.
A particularly interesting feature of the LRS 4432 scaler is-its latching capability : whenever a LOAD function is initiated, either by a specific CAMAC command or via the external front panel LOAD input, the content of all 32 scalers are 'frozen' (i.e. loaded into the 8 LSB latches and stored into one half of the memory), then read out of the scalers can be performed, sequentially or randomly.
It is to be noted that all inputs are disabled during less than 200 ns in response to a load command.
The user can also define his own LAM generation condition via a selection switch accessible through the side cover of the unit.
A test facility is provided that allows the user to check the scaler opera- tion without sending the full scale number of pulses into the unit; a speci- fic CAMAC function increments each byte by one count thus allowing complete scaler check to be done in 256 test cycles.
INPUTS
Signal Inputs 32, in two 2 x 17 pin front panel connectors.
'Input Levels Differential ECL or negative single ended TTL (MOD 100).
Customer ordering option for TTL single ended where the
scaler increments on the negative going transition.
Input Impedance 110 Ohm pin-to-pin with differential ECL
560 Ohm to + 5V with TTL single ended.
Minimum Input
Pulse Width 10 nsec,
Double. Pulse
Resolution < 30 nsec.
Maximum Frequency > 20 MHz.
Maximum Instanta-
neous Rate > 30 MHz.
COMMAND INPUTS
General The three command inputs have all front panel Lemo type
connectors; two bridged, high impedance inputs, for easy
daisy chaining of several modules; moreover all accept
both TTL as well as NIM pulses.
Load Input A LOAD pulse with > 15 nsec width, will disable inputs
for less than 200 nsec, and shift scaler contents into a
32 word x 24 bit buffer; the LOAD command can optionally
generate a LAM on the CAMAC dataway; also prepare memory
for readout loading the subaddress previously defined by
F (16) or Z.
Clear Input A CLEAR pulse with > 15 nsec width will disable inputs
for a duration of ~ 100 nsec and clear the 32 scalers.
Veto Input Disable inputs for the duration of the VETO (INHIBIT).
C Clears all scalers at S2.
Z Initialize the unit, i.e. all scalers, buffer and LAM
are cleared at S2; also define as zero the first sub-
address to be read.
I All scaler inputs are inhibited during CAMAC "INHIBIT"
command; the action is identical to that of the front
panel VETO input.
xi An X = 1 and Q = 1 response is generated for any of the
following functions.
L A Look-At-Me signal can be generated according to several
possible options described in the "Option switches"
paragraph.
N.F(O).A(O) Generate read-out of the selected channel; a Q response
is generated only if a LOAD had been previously performed.
Reload at S2 the output buffer memory.
N.F.(2).A(O) Generate sequential read-out of the memory starting from
the defined subaddress; increment subaddress of one at
S2; a Q response is generated only if a LOAD has been
previously performed; no Q response is generated in
correspondence with the 33rd channel.
N.F.(8).A(O) Tests LAM; generate Q response only if LAM was enabled.
N.F.(10).A(O) Test and clear LAM; a Q response is generated only if
LAM was enabled.
N.F(16).A(O) It performs different actions.
First of all, the normally sequential module read-out
can be modified by F(16); a LOAD command loads indeed
also the first subaddress to be read-out; this sub-
address has to be previously defined by F(16) on bit
Wl-W5 (or by Z). F(16) redefines then the starting
address; subsequent read-out may either continue through
only one cycle, or sequentially, using either a single
F(O) or F(2) commands or repetitive commands.
Other bits which can be loaded by F(16) and which are
meaningfull, are :
W9 : if = 1, performs a LOAD, equivalent to the front
panel LOAD;
W10: if = 1, performs a CLEAR, equivalent to the front
panel CLEAR;
Wll: if = 1, prepare for read-out the starting address
and enable Q and L;
W12: if = 1, performs increment test on all the 32
channels, for this test the 24 bits of each scaler.
are considered as three words of eight bits, the
three words are all incremented by one (this is in
order to reduce the complete test of the module to
only 256 cycles in total); generates permanently
"INHIBIT".
Option Switches :
A set of six internal switches allows the customer for
selection of the following options :
1 - Disable latching; the Model 4432 works then as a
normal (not latching) scaler. (LGD)
2 - Overflow condition switch; when on, overflow condi-
tion occurs when bit 24 and bit 16 of any scaler
are on; when off, overflow condition occurs when
bit 16 of any scaler is on; LAM generation is still
conditioned by switch 4 position.(024)
3 - Enable automatic generation of a WAD and CLEAR
sequence as soon as overflow occurs according to
switch 2 position.(LCO)
4 - Enable LAM generation at overflow.(LRO)
5 - Enable LAM generation when data ready (read out can
be effected).(LDR)
6 - Enable to clear LAM after a read-out accomplished by
F (0) or F (2) . (CLR)
Power Consumption :
+ 6V, <3 A ; - 6V, 3OmA (TTL version)
33OmA (ECL version)