* 4 Independent Flash ADCS, 4 Bits plus Overflow
* 100 MHz with Sampling Times down to 4 nsec
* Variable Voltage Range
* Front Panel Fast Data Output
* External Strobe or Free Running
The Model 4504 has been designed for applications where digital representations of analog signals are required in fast trigger logic systems.
The unit contains four identical channels each of which accepts an analog voltage of up to 5 V. Upon receipt of a strobe pulse, each input signal is converted to a 4-bit digital word. The inputs may be sampled at a frequency of up to 100 MHz with sampling times as short as 4 ns.
The accepted voltage range of the 4504 may be tailored to the characteristics of the input signals. This is done by adjusting two voltage levels, common for the four channels, via two 8-bit CAMAC programmable DAC's. Each voltage level may be set between - 2.5 V and + 2.5 V. The voltage difference between these two levels gives the analog voltage range which will be quantized into 15 equally spaced intervals and finally coded into a 4-bit binary digital word.
A digital overflow output is provided for each channel to indicate that the input pulse has exceeded the positive full scale limit. In case of an overflow, that channels's overflow bit is set to one. The four bits of the corresponding digital output word can be forced to one or zero depending on the position of a side switch.
A strobe output timed with the flash ADC outputs is also provided for use in subsequent logic operations.
Typical applications for this unit includes situations where the analog majority level provided by several ECLine units (4417, 4448, 4532) has to be converted into a digital information for use with the ECLine Model 4508 fast look up memory.
When used with pulses from photomultipliers, wire chambers or other detectors, the 4504 acts as a multithreshold discriminator encoding the pulse amplitude into the four output bits. The 4504 measures voltage. To digitize charge, the input should be preceeded by an integrator. PRELIMINARY TECHNICAL SPECIFICATIONS CAMAC ECLine MODEL 4504 4-CHANNEL 4-BIT FLASH ADC
INPUT CHARACTERISTICS
Analog Inputs (A): Four, one per channel; Lemo type connectors; 50 Ohm input
impedance; direct coupled; minimum input pulse width
10 nsec.
Strobe Input (STI): One, common to the four channels; two pin connector;
110 Ohm input impedance; accepts complementary ECL
pulses; minimum input width 4 nsec; maximum frequency
100 MHz; the trailing edge of the strobe pulse will
hold the digital output until the next strobe pulse
arrives.
Veto Input (VETO): One in a two pin front panel connector; 110 Ohm input
impedance; accepts complementary ECL pulses; vetoes
the strobe input during its width.
OUTPUT CHARACTERISTICS
Digital Outputs (OUT): 16, four per channel, in a 2 x 17 pin front panel
connector; provides complementary ECL pulses; the
four outputs represent a four bit binary word giving
the digital translation of the analog value at the
input; the digital outputs change state in
correspondence with the trailing edge of the strobe
pulse and hold until the next strobe pulse is applied.
Overflow Outputs 4, one per channel, in a 2 x 4 pin front panel
(POS OVF): connector; provide complementary ECL pulses behaving
as the Digital Outputs above and indicate that the
input signals have exceeded the positive full scale
limit.
Strobe Outputs (STO): 4 in total; two in a 2 x 2 pin front panel connector
providing complementary ECL pulses; two in front panel
Lemo type connectors; high output impedance (current
source); generate NIM level pulses when terminated in
502 ; produce a pulse, suitable as a strobe for
subsequent logic operations, which is triggered by the
strobe input and timed with the digital outputs; the
width is adjustable by a front panel potentiometer
(STW) in the range 5 to 30 nsec.
CAMAC COMMANDS AND FUNCTIONS
C: Generates a strobe during S2 time. This function is
not affected by I or VETO input and may be disabled by
a side panel switch. The digital outputs will be set
depending on the analog value of the inputs; in parti-
cular, if the inputs are disconnected all the digital
outputs will correspond to 0 V at the inputs. The
output logic state will be determined by the VL and VH
reference voltages.
X, Q: X = 1 and Q = 1 response are generated for any of the
following functions:
F(O)*A(O): Read digital outputs; R1 to R16, four bits per
channel.
F(O)*A(1): Read digital overflow, Rl to R4, one bit per channel.
F(16)*A(O): Write Low Reference Voltage (VL) on 8 bits; range
from - 2550 mV to + 2550 mV in steps of 20 mV.
F(16)*A(1): Same as above but for the High Reference Voltage (VH).
F(25)*A(0,1): Equivalent to C.
GENERAL
Test Points: Two front panel test points allow measurements of VL
and VH in a ratio 1:1; output impedance 7.5 K Ohm.
Strobe Switch: A front panel switch allows the strobe be generated
either by the front panel strobe input (STRB) , or by
an internal free running oscillator (SAMP) whose
frequency is adjustable by a front panel potentiometer
(FREQ) from 20 to 100 MHz; the veto input is active in
both cases.
Overflow Switch: A side switch (OUT STATE AT OVERFLOW) allows the
setting of all digital outputs to one or zero when an
overflow occurs.
Clear Switch: A side switch (CLEAR) allow the CAMAC clear function
to be disabled.
Most Significant Bit: A side switch (MSB) selects W8/R8 or W16/Rl6 as the
MSB for data written/read from VL and VH.
Minimum ADC Resolution: 40 mV/step.
Transit Time: Strobe (trailing edge) to digital outputs ~15 nsec.
Power Consumption: +6 V: 1.1 A
-6 V: 1.5 A
+24 V: 6 mA
Packaging: Single width CAMAC standard module.