LeCroy 4532 32-Channel Maj. Logic, ECL

CAMAC Model 4532 32 Input Majority Logic Unit

The ECLine Model 4532 answers most of the majority logic problems encountered in modern High Energy Physics Experiments.

The Model 4532 calculates the multiplicity value from 32 logic channels and presents the result as a current proportional to the number of inputs up to a maximum of 16. These may be either in- dividual inputs or clusters (i.e. adjacent inputs are counted as one input) as determined by a side switch. The multiplicity calculation can either be performed on the overlap of input pulses during a time determined by an externally applied gate (e.g. with photomultipliers), or on latched levels which are set by inputs occurring within a predetermined time window (e.g. for use with propor- tional chambers). In the latter mode, the analog output will increase as each pulse arrives at the inputs. The time window can be either internally generated or externally provided. The internal time window is self-triggered by the first input pulse arriving after a previous reset. A front panel potentiometer permits adjustment of the time window.

In addition to the front panel outputs, the Model 4532 also stores the input information which ar- rived during the time window in a CAMAC addressable 32-bit register. In both the overlap Memory Disable and latching Memory Enable modes, a front panel output provides a two by two OR of the gated inputs. The OR is performed on channels 1 and 2, 3 and 4, etc. In Overlap mode, the outputs will be pulses having a width determined by the input pulse widths, while in Latching mode the outputs will be levels set by the leading edge of the input pulses and reset by the CAMAC or front panel fast reset functions.

The Model 4532 analog output is provided on two paralleled connectors to permit the cascading of several majority units and extending the multiplicity calculation beyond 32 inputs.

The analog output is designed to be used as input to a variable threshold discriminator, or to the Model 4504 Flash ADC for conversion into a four-bit binary word.

CAMAC Model 4532 32 Input Majority Logic Unit
SPECIFICATIONS

INPUT CHARACTERISTICS

All inputs accept differential ECL level (- 0.8 V, - 1.7 V) into 1 1 0 ohm input impedance (high input impedance is possible by removing socket mounted terminators).

Data Input (IN):

32 in two 34 pin front panel connectors; minimum input pulse width 6 nsec, maximum width DC.

Reset Input (RTI):

Fast reset of the input registers; generates a reset of the analog majority output and of the comparator outputs (MDO, DMO). When the analog output is cascaded with other units, the RTI only resets the contribution from the modules that received the RTI. Minimum input pulse width 6 nsec, maximum width DC. In Memory Disable mode, the RTI is inhibited.

Gate Input (GAI):

Normally open when unconnected. Normally closed when connected to a cable providing standard ECLine levels. In Memory Disable mode, data pulses having an overlap with the GAI will contribute to the outputs. In Memory Enable mode, data pulses having their leading edge inside the GAI time will be accepted and stored. By deriving the GAI from the DMO, an internally generated time window is possible. Minimum overlap time width with input pulses for majority decisions, 10 nsec. Minimum overlap time width with input pulses for logical OR's, 3 nsec; maximum width DC.

Cluster Carry (CCI):

When Cluster Selection is Enabled, receives the carry information on the cluster from the Cluster Carry Output (CCO) of any adjacent majority logic unit.

Analog Majority Input/Output (AMIO):

Two bridged front panel Lemo type connectors; high impedance current source; generates a current proportional to the input multiplicity at the rate of 3.2 mA per hit (or 80 mV per hit into 25 ohms). The AMIO connectors can be used for daisy chaining of analog majority information within a group of similar units. Transit time between AMIO connectors 2 nsec. Unused output must be terminated with 50 ohms.

OUTPUT CHARACTERISTICS

All logic outputs provide complementary ECL levels (- 0.8 V, - 1.7 V) and are capable of driving differential 1 1 0 ohm loads.

Data Outputs (OUT):

16 in a 34 pin front panel connector. Each output corresponds to the logical OR of two channels (respectively, 1 and 2, 3 and 4,..., 31 and 32). In Memory Disable mode, provides pulses corresponding to an overlap coincidence bet- ween the gate pulse and the data inputs. In Memory Enable mode, provides levels started by the coincidence between the gate pulse and the leading edge of the data pulses.

OR Output (ORO):

Provides the logical OR of the 32 channels, otherwise, behaves as data outputs.

Strobe Output (STO):

Provides a pulse, suitable for strobing of subsequent logic units, at the end of the gate in- put and delayed by the internal transit time (6 nsec). Width adjustable from 10 to 25 nsec by a trimmer (STROBE WIDTH) accessible from the side of the module.

Majority Discriminated Output (MDO):

The AMIO input/output is internally used as input to an adjustable threshold comparator providing the MDO output. Threshold adjustable from 1 to 16 hits by a front panel potentiometer (MA THR). The output will be a pulse or a level depending on the selected operating mode.

Delayed Majority Output (DMO):

Reproduces the output MDO above, after an adjustable delay. A switch on the side of the module (DM RANGE) selects one of two delay ranges; 10-100 nsec or 50-1000 nsec. A front panel potentiometer (DMO DELAY RANGE) permits continuous adjust- ment. The DMO is cleared as soon as the MDO is cleared.

Cluster Carry (CCO):

When Cluster Selection is Enabled, indicates that Output channel 32 was hit for use in conjunction with channel 1 of a logically adjacent cluster logic in another 4532 module (CCI input).

CAMAC COMMANDS

Z, C

Clears data memory and LAM at S2 time.

L

A Look-At-Me signal is generated (in Memory Enable mode only) at the end of the gate in- put if the OR output is set. The LAM may be enabled or disabled by the LAM enable switch accessible on the side of the module.

X

An X= 1 response is generated for any executable function.

Q

A Q = 1 response is generated for any executable function in Memory Enable mode only.

F(O)-A(O), A(l)

Read input pattern. A(O): channels 1 to 16, A(l): channels 17 to 32.
A Q response is generated in Memory Enable mode only.

F(1)-A(O) Read status register:

R1 = 1 if LAM is ON
R2 = 1 it LAM Enable switch is ON
R3 = 1 if MEMORY Enable switch is ON
R4 = 1 if CLUSTER Enable switch is ON
Q response is always generated.

F(2)-A(O)

Read input pattern, channels 1 to 16.
Q response is generated in Memory Enable mode only.

F(2)-A(l)

Read input pattern, channels 17 to 32, and clears the 32 channel data memory and LAM at S2.
Q response is generated in Memory Enable mode only.

F(8)-A(O)

Test LAM: a Q response is generated if L is ON.

F(9)-A(O)

Clears the data memory and LAM at S2.
Q response is generated in Memory Enable mode only.

F(10)-A(O)

Test and clear LAM, clears LAM at S2 time.
Q response is generated if L is ON. The clear LAM operation is not executed if Q response is missing.

GENERAL

Mode Selection:

A Memory Enable switch, accessible on the side of the module, selects one of the following modes:

Memory Disable: Functions are disabled; the multiplicity calculation is performed on the overlap of the data inputs.
Memory Enable: The data inputs are latched; the multiplicity is determined by the number of leading edges of data input pulses occurring during the gate time. In this mode the unit needs to be cleared either by the reset input (RTI) or by a resetting function.

Cluster Selection:

The Cluster Enable switch, accessible on the side of the module, determines one of the two following modes:

Cluster Disable: Each data input provides one hit on the Analog Majority Output AMIO; the Cluster Carry Input (CCI) is disabled;
Cluster Enable: Any group of adjacent input data pulses will be considered as a single hit. Provision has been made for the clusters to extend beyond the 32 inputs. If an input is present on the logically adjacent channel to input 1 of this unit but is located in another unit, the CCI can be used to indicate its presence. The CCO of this module indicates that channel 32 of this module is present.

Transit Times:

Data IN to AMIO

16 nsec

AMIO to MDO output

5 nsec

End of gate IN to Strobe OUT

6 nsec

Data IN to Data OUT

12 nsec

Data IN to OR OUT

16 nsec

Reset IN to Data OUT

20 nsec

Reset IN to OR OUT

24 nsec

Data IN 32 to Cluster Carry OUT

11 nsec

Cluster Carry IN to Data IN

12 nsec

Gate pulse must precede Data pulse by at least 7 nsec.

Current Requirements:

+ 6 V at 200 mA
- 6 V at < 3.6 A (3 A when empty)
+ 24 V at 5 mA
-24 V at 7 mA

Packaging:

Single-width standard CAMAC module.

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INPUT CHARACTERISTICS
All inputs accept differential ECL level (- 0.8 V, - 1.7 V) into 1 1 0 ohm input impedance (high input impedance is possible by removing socket mounted terminators).
Data Input (IN):	32 in two 34 pin front panel connectors; minimum input pulse width 6 nsec, maximum width DC.
Reset Input (RTI):	Fast reset of the input registers; generates a reset of the analog majority output and of the comparator outputs (MDO, DMO). When the analog output is cascaded with other units, the RTI only resets the contribution from the modules that received the RTI. Minimum input pulse width 6 nsec, maximum width DC. In Memory Disable mode, the RTI is inhibited.
Gate Input (GAI):	Normally open when unconnected. Normally closed when connected to a cable providing standard ECLine levels. In Memory Disable mode, data pulses having an overlap with the GAI will contribute to the outputs. In Memory Enable mode, data pulses having their leading edge inside the GAI time will be accepted and stored. By deriving the GAI from the DMO, an internally generated time window is possible. Minimum overlap time width with input pulses for majority decisions, 10 nsec. Minimum overlap time width with input pulses for logical OR's, 3 nsec; maximum width DC.
Cluster Carry (CCI):	When Cluster Selection is Enabled, receives the carry information on the cluster from the Cluster Carry Output (CCO) of any adjacent majority logic unit.
Analog Majority Input/Output (AMIO):	Two bridged front panel Lemo type connectors; high impedance current source; generates a current proportional to the input multiplicity at the rate of 3.2 mA per hit (or 80 mV per hit into 25 ohms). The AMIO connectors can be used for daisy chaining of analog majority information within a group of similar units. Transit time between AMIO connectors 2 nsec. Unused output must be terminated with 50 ohms.
OUTPUT CHARACTERISTICS
All logic outputs provide complementary ECL levels (- 0.8 V, - 1.7 V) and are capable of driving differential 1 1 0 ohm loads.
Data Outputs (OUT):	16 in a 34 pin front panel connector. Each output corresponds to the logical OR of two channels (respectively, 1 and 2, 3 and 4,..., 31 and 32). In Memory Disable mode, provides pulses corresponding to an overlap coincidence bet- ween the gate pulse and the data inputs. In Memory Enable mode, provides levels started by the coincidence between the gate pulse and the leading edge of the data pulses.
OR Output (ORO):	Provides the logical OR of the 32 channels, otherwise, behaves as data outputs.
Strobe Output (STO):	Provides a pulse, suitable for strobing of subsequent logic units, at the end of the gate in- put and delayed by the internal transit time (6 nsec). Width adjustable from 10 to 25 nsec by a trimmer (STROBE WIDTH) accessible from the side of the module.
Majority Discriminated Output (MDO):	The AMIO input/output is internally used as input to an adjustable threshold comparator providing the MDO output. Threshold adjustable from 1 to 16 hits by a front panel potentiometer (MA THR). The output will be a pulse or a level depending on the selected operating mode.
Delayed Majority Output (DMO):	Reproduces the output MDO above, after an adjustable delay. A switch on the side of the module (DM RANGE) selects one of two delay ranges; 10-100 nsec or 50-1000 nsec. A front panel potentiometer (DMO DELAY RANGE) permits continuous adjust- ment. The DMO is cleared as soon as the MDO is cleared.
Cluster Carry (CCO):	When Cluster Selection is Enabled, indicates that Output channel 32 was hit for use in conjunction with channel 1 of a logically adjacent cluster logic in another 4532 module (CCI input).
CAMAC COMMANDS
Z, C	Clears data memory and LAM at S2 time.
L	A Look-At-Me signal is generated (in Memory Enable mode only) at the end of the gate in- put if the OR output is set. The LAM may be enabled or disabled by the LAM enable switch accessible on the side of the module.
X	An X= 1 response is generated for any executable function.
Q	A Q = 1 response is generated for any executable function in Memory Enable mode only.
F(O)-A(O), A(l)	Read input pattern. A(O): channels 1 to 16, A(l): channels 17 to 32. A Q response is generated in Memory Enable mode only.
F(1)-A(O) Read status register:	R1 = 1 if LAM is ON R2 = 1 it LAM Enable switch is ON R3 = 1 if MEMORY Enable switch is ON R4 = 1 if CLUSTER Enable switch is ON Q response is always generated.
F(2)-A(O)	Read input pattern, channels 1 to 16. Q response is generated in Memory Enable mode only.
F(2)-A(l)	Read input pattern, channels 17 to 32, and clears the 32 channel data memory and LAM at S2. Q response is generated in Memory Enable mode only.
F(8)-A(O)	Test LAM: a Q response is generated if L is ON.
F(9)-A(O)	Clears the data memory and LAM at S2. Q response is generated in Memory Enable mode only.
F(10)-A(O)	Test and clear LAM, clears LAM at S2 time. Q response is generated if L is ON. The clear LAM operation is not executed if Q response is missing.
GENERAL
Mode Selection:	A Memory Enable switch, accessible on the side of the module, selects one of the following modes: Memory Disable: Functions are disabled; the multiplicity calculation is performed on the overlap of the data inputs. Memory Enable: The data inputs are latched; the multiplicity is determined by the number of leading edges of data input pulses occurring during the gate time. In this mode the unit needs to be cleared either by the reset input (RTI) or by a resetting function.
Cluster Selection:	The Cluster Enable switch, accessible on the side of the module, determines one of the two following modes: Cluster Disable: Each data input provides one hit on the Analog Majority Output AMIO; the Cluster Carry Input (CCI) is disabled; Cluster Enable: Any group of adjacent input data pulses will be considered as a single hit. Provision has been made for the clusters to extend beyond the 32 inputs. If an input is present on the logically adjacent channel to input 1 of this unit but is located in another unit, the CCI can be used to indicate its presence. The CCO of this module indicates that channel 32 of this module is present.
Transit Times:	Data IN to AMIO	16 nsec
	AMIO to MDO output	5 nsec
	End of gate IN to Strobe OUT	6 nsec
	Data IN to Data OUT	12 nsec
	Data IN to OR OUT	16 nsec
	Reset IN to Data OUT	20 nsec
	Reset IN to OR OUT	24 nsec
	Data IN 32 to Cluster Carry OUT	11 nsec
	Cluster Carry IN to Data IN	12 nsec
	Gate pulse must precede Data pulse by at least 7 nsec.
Current Requirements:	+ 6 V at 200 mA - 6 V at < 3.6 A (3 A when empty) + 24 V at 5 mA -24 V at 7 mA
Packaging:	Single-width standard CAMAC module.