NOTE:  The files listed in this table are only accessable from on-site at FNAL

ECO Number	Purpose	Drawings / Other Documentation
0001	Several J26 outputs used as strobes to access various board resources need to be synchronous with DSP clock H3.	MSWord
0002	Eliminate 24nSec Clock Noise on  L2A pin of TDC chips 0-7	MSWord
0003	Correct a power-up condition which could cause buffer chips P2, PQ6 to destruct.
0004	Correct a board reset condition which could cause buffer chips P2, PQ6 to destruct.
0005	Replace Q3 component which has known defect which can cause TDC boards to hang the VME bus.
0006	Glitch on RD_SRAM* output of J26 during VME reads can result in corrupted data to be read.
0007	Correct a board design error which can result in incorrect data to be read from the VME FIFO during a DSP write cycle.
0008 PENDING	To prevent erroneous bunch crossing register values caused by noise pick-up on signal L1_ACCEPT_12 from WIRE_DATA signals.
0009	Provide sufficient drive current for DSP data and address lines.

NOTE:  The files listed in this table are only accessable from on-site at FNAL

    14-MAR-2001 mlb